From d3dc8238eefeceaa9fa742252380d527acb6017c Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Fri, 12 Aug 2022 14:44:57 +0100
Subject: [PATCH]

---
 openpower/sv/svp64_quirks.mdwn | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index e94681854..1ae1e7604 100644
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -13,6 +13,8 @@ as a concept became popular.
    just because it is prefixed (semantic caveats below)
 3. A hardware-level for-loop (the prefix) makes vector elements
    100% synonymous with scalar instructions (the suffix)
+4. Exactly as with Scalar RISC ISAs, the uniformity does produce
+   "holes" in the encoding or some strange combinations.
 
 How can a Vector ISA even exist when no actual Vector instructions
 are permitted to be added? It comes down to the strict RISC abstraction.
-- 
2.30.2