From d3f7cc8ed2a81480b232fe736bde3e786dde9e59 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 2 Oct 2019 03:50:20 +0000
Subject: [PATCH] back.rtlil: sign of rhs and lhs of ${sshr,sshl,pow} don't
 need to match.

---
 nmigen/back/rtlil.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index 298d2f9..7424c9d 100644
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -485,7 +485,7 @@ class _RHSValueCompiler(_ValueCompiler):
         lhs, rhs = value.operands
         lhs_bits, lhs_sign = lhs.shape()
         rhs_bits, rhs_sign = rhs.shape()
-        if lhs_sign == rhs_sign:
+        if lhs_sign == rhs_sign or value.op in ("<<", ">>", "**"):
             lhs_wire = self(lhs)
             rhs_wire = self(rhs)
         else:
-- 
2.30.2