From d40119f4225051e3acd4561beac61368f7922259 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 15 May 2023 16:07:04 +0100 Subject: [PATCH] in DCT/FFT 3-in 2-out set had to make RT same source-dest EXTRA puzzlingly this frees up 2 bits but still cannot do EXTRA3 due to needing 1 bit for selecting RS=RT+MAXVL or RS=RC --- openpower/isatables/RM-1P-3S1D.csv | 10 +++++----- src/openpower/sv/sv_analysis.py | 16 ++++++++-------- 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/openpower/isatables/RM-1P-3S1D.csv b/openpower/isatables/RM-1P-3S1D.csv index f09256c8..505572d4 100644 --- a/openpower/isatables/RM-1P-3S1D.csv +++ b/openpower/isatables/RM-1P-3S1D.csv @@ -45,11 +45,11 @@ dsrd,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,CR0,0 dsrd.,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,CR0,0 pcdec,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,CR0,0 ternlogi,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RT,RA,RB,RT,RT,0,CR0,0 -ffmsubs,NORMAL,,1P,EXTRA2,NO,d:FRT;d:CR1,s:FRT,s:FRB,s:FRA,FRT,FRB,FRA,FRT,0,CR1,0 -ffmadds,NORMAL,,1P,EXTRA2,NO,d:FRT;d:CR1,s:FRT,s:FRB,s:FRA,FRT,FRB,FRA,FRT,0,CR1,0 -ffnmsubs,NORMAL,,1P,EXTRA2,NO,d:FRT;d:CR1,s:FRT,s:FRB,s:FRA,FRT,FRB,FRA,FRT,0,CR1,0 -ffnmadds,NORMAL,,1P,EXTRA2,NO,d:FRT;d:CR1,s:FRT,s:FRB,s:FRA,FRT,FRB,FRA,FRT,0,CR1,0 -fdmadds,NORMAL,,1P,EXTRA2,NO,d:FRT;d:CR1,s:FRT,s:FRB,s:FRA,FRT,FRB,FRA,FRT,0,CR1,0 +ffmsubs,NORMAL,,1P,EXTRA2,NO,s:FRT;d:FRT;d:CR1,s:FRB,s:FRA,0,FRT,FRB,FRA,FRT,0,CR1,0 +ffmadds,NORMAL,,1P,EXTRA2,NO,s:FRT;d:FRT;d:CR1,s:FRB,s:FRA,0,FRT,FRB,FRA,FRT,0,CR1,0 +ffnmsubs,NORMAL,,1P,EXTRA2,NO,s:FRT;d:FRT;d:CR1,s:FRB,s:FRA,0,FRT,FRB,FRA,FRT,0,CR1,0 +ffnmadds,NORMAL,,1P,EXTRA2,NO,s:FRT;d:FRT;d:CR1,s:FRB,s:FRA,0,FRT,FRB,FRA,FRT,0,CR1,0 +fdmadds,NORMAL,,1P,EXTRA2,NO,s:FRT;d:FRT;d:CR1,s:FRB,s:FRA,0,FRT,FRB,FRA,FRT,0,CR1,0 fmsubs,NORMAL,,1P,EXTRA2,NO,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0 fmadds,NORMAL,,1P,EXTRA2,NO,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0 fnmsubs,NORMAL,,1P,EXTRA2,NO,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0 diff --git a/src/openpower/sv/sv_analysis.py b/src/openpower/sv/sv_analysis.py index 072742c6..6b9c9b51 100644 --- a/src/openpower/sv/sv_analysis.py +++ b/src/openpower/sv/sv_analysis.py @@ -597,10 +597,10 @@ def extra_classifier(insn_name, value, name, res, regs): elif value == 'RM-1P-3S1D': res['Etype'] = 'EXTRA2' # RM EXTRA2 type if regs == ['FRT', 'FRB', 'FRA', 'FRT', '', 'CR1']: # ffmadds/fdmadds - res['0'] = 'd:FRT;d:CR1' # FRT,CR1: Rdest1_EXTRA2 - res['1'] = 's:FRT' # FRT: Rsrc1_EXTRA2 - res['2'] = 's:FRB' # FRB: Rsrc2_EXTRA2 - res['3'] = 's:FRA' # FRA: Rsrc3_EXTRA2 + res['0'] = 's:FRT;d:FRT;d:CR1' # FRT,CR1: Rdest1_EXTRA2 + res['1'] = 's:FRB' # FRB: Rsrc1_EXTRA2 + res['2'] = 's:FRA' # FRA: Rsrc2_EXTRA2 + res['3'] = '' # empty elif regs == ['RA', 'RB', 'RC', 'RT', '', '']: # madd* res['0'] = 'd:RT' # RT,CR0: Rdest1_EXTRA2 res['1'] = 's:RA' # RA: Rsrc1_EXTRA2 @@ -612,15 +612,15 @@ def extra_classifier(insn_name, value, name, res, regs): res['2'] = 's:RB' # RT: Rsrc2_EXTRA2 res['3'] = 's:RC' # RT: Rsrc3_EXTRA2 elif regs == ['RA', 'RB', 'RT', 'RT', '', 'CR0']: # overwrite 3-in - res['0'] = 'd:RT;d:CR0' # RT,CR0: Rdest1_EXTRA2 + res['0'] = 's:RT;d:RT;d:CR0' # RT,CR0: Rdest1_EXTRA2 res['1'] = 's:RA' # RA: Rsrc1_EXTRA2 res['2'] = 's:RB' # RT: Rsrc2_EXTRA2 - res['3'] = 's:RT' # RT: Rsrc3_EXTRA2 + res['3'] = '' # empty elif regs == ['RA', 'RB', 'RT', 'RT', '', '']: # maddsubrs - res['0'] = 'd:RT' # RT: Rdest1_EXTRA2 + res['0'] = 's:RT;d:RT' # RT: Rdest1_EXTRA2 res['1'] = 's:RA' # RA: Rsrc1_EXTRA2 res['2'] = 's:RB' # RT: Rsrc2_EXTRA2 - res['3'] = 's:RT' # RT: Rsrc3_EXTRA2 + res['3'] = '' # empty elif insn_name == 'isel': res['0'] = 'd:RT' # RT: Rdest1_EXTRA2 res['1'] = 's:RA' # RA: Rsrc1_EXTRA2 -- 2.30.2