From d401a033b3a64e8408436ad5a65e27d0d48e71a0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 4 Jun 2020 21:01:11 +0100 Subject: [PATCH] use common TestCase class in logical --- src/soc/fu/logical/test/test_pipe_caller.py | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py index c74dbe45..07ef8150 100644 --- a/src/soc/fu/logical/test/test_pipe_caller.py +++ b/src/soc/fu/logical/test/test_pipe_caller.py @@ -11,18 +11,12 @@ from soc.decoder.selectable_int import SelectableInt from soc.simulator.program import Program from soc.decoder.isa.all import ISA +from soc.fu.test.common import TestCase from soc.fu.logical.pipeline import LogicalBasePipe from soc.fu.logical.pipe_data import LogicalPipeSpec import random -class TestCase: - def __init__(self, program, regs, sprs, name): - self.program = program - self.regs = regs - self.sprs = sprs - self.name = name - def get_cu_inputs(dec2, sim): """naming (res) must conform to LogicalFunctionUnit input regspec """ @@ -89,8 +83,8 @@ class LogicalTestCase(FHDLTestCase): super().__init__(name) self.test_name = name - def run_tst_program(self, prog, initial_regs=[0] * 32, initial_sprs={}): - tc = TestCase(prog, initial_regs, initial_sprs, self.test_name) + def run_tst_program(self, prog, initial_regs=None, initial_sprs=None): + tc = TestCase(prog, self.test_name, initial_regs, initial_sprs) self.test_data.append(tc) def test_rand(self): -- 2.30.2