From d40644a39c4ab8c77bad492e7f76368fc5665706 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 1 Jun 2020 23:06:00 +0100 Subject: [PATCH] remove reading port 3 for CR pipeline. RS moved to port 1 --- src/soc/fu/compunits/test/test_cr_compunit.py | 4 ---- src/soc/fu/cr/test/test_pipe_caller.py | 6 ------ 2 files changed, 10 deletions(-) diff --git a/src/soc/fu/compunits/test/test_cr_compunit.py b/src/soc/fu/compunits/test/test_cr_compunit.py index b1b6332d..cf8572e9 100644 --- a/src/soc/fu/compunits/test/test_cr_compunit.py +++ b/src/soc/fu/compunits/test/test_cr_compunit.py @@ -43,13 +43,9 @@ class CRTestRunner(TestRunner): # RA/RC reg1_ok = yield dec2.e.read_reg1.ok - reg3_ok = yield dec2.e.read_reg3.ok if reg1_ok: data1 = yield dec2.e.read_reg1.data res['a'] = sim.gpr(data1).value - if reg3_ok: - data1 = yield dec2.e.read_reg3.data - res['a'] = sim.gpr(data1).value # RB (or immediate) reg2_ok = yield dec2.e.read_reg2.ok diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py index e0d529b2..ffe6bad5 100644 --- a/src/soc/fu/cr/test/test_pipe_caller.py +++ b/src/soc/fu/cr/test/test_pipe_caller.py @@ -169,12 +169,6 @@ class TestRunner(FHDLTestCase): cr3 = simulator.crl[cr3_sel].get_range().value yield alu.p.data_i.cr_c.eq(cr3) - reg3_ok = yield dec2.e.read_reg3.ok - if reg3_ok: - reg3_sel = yield dec2.e.read_reg3.data - reg3 = simulator.gpr(reg3_sel).value - yield alu.p.data_i.a.eq(reg3) - reg1_ok = yield dec2.e.read_reg1.ok if reg1_ok: reg1_sel = yield dec2.e.read_reg1.data -- 2.30.2