From d42161569bfaad5f0703f67d41634fd460719c1b Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Thu, 28 May 2020 20:58:39 +0200 Subject: [PATCH] indention --- src/soc/experiment/l0_cache.py | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py index 40e73a3d..1e4177e4 100644 --- a/src/soc/experiment/l0_cache.py +++ b/src/soc/experiment/l0_cache.py @@ -189,22 +189,22 @@ class DataMerger(Elaboratable): self.data_i = Array(ul) self.data_o = DataMergerRecord() - def elaborate(self, platform): - m = Module() - comb = m.d.comb - #(1) pick a row - m.submodules.pick = pick = PriorityEncoder(self.array_size) + def elaborate(self, platform): + m = Module() + comb = m.d.comb + #(1) pick a row + m.submodules.pick = pick = PriorityEncoder(self.array_size) + for j in range(self.array_size): + comb += pick.i[j].eq(self.addr_match_i[j].bool()) + valid = ~pick.n + idx = pick.o + #(2) merge + with m.If(valid): + l = [] for j in range(self.array_size): - comb += pick.i[j].eq(self.addr_match_i[j].bool()) - valid = ~pick.n - idx = pick.o - #(2) merge - with m.If(valid): - l = [] - for j in range(self.array_size): - select = self.addr_match_i[idx][j] - l.append(Mux(select, self.data_i[j], 0)) - comb += self.data_o.eq(ortreereduce(l)) + select = self.addr_match_i[idx][j] + l.append(Mux(select, self.data_i[j], 0)) + comb += self.data_o.eq(ortreereduce(l)) class LDSTPort(Elaboratable): -- 2.30.2