From d43c3bbe71f8fc69280b7236686e4c42fbb854bb Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 29 Sep 2018 04:05:00 +0100 Subject: [PATCH] reorganise from moving sv_pred_* and sv_reg_* tables into processor_t --- riscv/insn_template_sv.cc | 18 ++++++------- riscv/sv.cc | 56 +++++++++++++++++++++++---------------- riscv/sv_decode.h | 11 +++++--- 3 files changed, 50 insertions(+), 35 deletions(-) diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc index 6fa9623..4b7a41a 100644 --- a/riscv/insn_template_sv.cc +++ b/riscv/insn_template_sv.cc @@ -15,36 +15,36 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc) // need to know if register is used as float or int. // REGS_PATTERN is generated by id_regs.py (per opcode) unsigned int floatintmap = REGS_PATTERN; - sv_insn_t insn(bits, floatintmap); + sv_insn_t insn(p, bits, floatintmap); reg_t predicate = 0; // identify which regs have had their CSR entries set as vectorised. // really could do with a macro for-loop here... oh well... // integer ops, RD, RS1, RS2, RS3 (use sv_int_tb) bool vectorop = #ifdef USING_RD - check_reg(true, s_insn.rd()) | + insn.check_reg(true, s_insn.rd()) | #endif #ifdef USING_RS1 - check_reg(true, s_insn.rs1()) | + insn.check_reg(true, s_insn.rs1()) | #endif #ifdef USING_RS2 - check_reg(true, s_insn.rs2()) | + insn.check_reg(true, s_insn.rs2()) | #endif #ifdef USING_RS2 - check_reg(true, s_insn.rs3()) | + insn.check_reg(true, s_insn.rs3()) | #endif // fp ops, RD, RS1, RS2, RS3 (use sv_fp_tb) #ifdef USING_FRD - check_reg(false, s_insn.frd()) | + insn.check_reg(false, s_insn.frd()) | #endif #ifdef USING_FRS1 - check_reg(false, s_insn.frs1()) | + insn.check_reg(false, s_insn.frs1()) | #endif #ifdef USING_FRS2 - check_reg(false, s_insn.rs2()) | + insn.check_reg(false, s_insn.rs2()) | #endif #ifdef USING_FRS2 - check_reg(false, s_insn.rs3()) | + insn.check_reg(false, s_insn.rs3()) | #endif false; // save a few cycles by |ing the checks together. diff --git a/riscv/sv.cc b/riscv/sv.cc index b0453e2..4341363 100644 --- a/riscv/sv.cc +++ b/riscv/sv.cc @@ -1,17 +1,43 @@ #include "sv.h" #include "sv_decode.h" -bool sv_check_reg(bool intreg, uint64_t reg) +sv_pred_entry* sv_insn_t::get_predentry(uint64_t reg, bool intreg) { + // okaay so first determine which map to use. intreg is passed + // in (ultimately) from id_regs.py's examination of the use of + // FRS1/RS1, WRITE_FRD/WRITE_RD, which in turn gets passed + // in from sv_insn_t::fimap... + sv_pred_entry *r; + if (intreg) + { + return &p->get_state()->sv_pred_int_tb[reg]; + } + else + { + return &p->get_state()->sv_pred_fp_tb[reg]; + } +} + +sv_reg_entry* sv_insn_t::get_regentry(uint64_t reg, bool intreg) +{ + // okaay so first determine which map to use. intreg is passed + // in (ultimately) from id_regs.py's examination of the use of + // FRS1/RS1, WRITE_FRD/WRITE_RD, which in turn gets passed + // in from sv_insn_t::fimap... sv_reg_entry *r; if (intreg) { - r = &sv_int_tb[reg]; + return &p->get_state()->sv_int_tb[reg]; } else { - r = &sv_fp_tb[reg]; + return &p->get_state()->sv_fp_tb[reg]; } +} + +bool sv_insn_t::sv_check_reg(bool intreg, uint64_t reg) +{ + sv_reg_entry *r = get_regentry(reg, intreg); if (r->elwidth != 0) { // XXX raise exception @@ -45,15 +71,8 @@ uint64_t sv_insn_t::remap(uint64_t reg, bool intreg, int &voffs) // in (ultimately) from id_regs.py's examination of the use of // FRS1/RS1, WRITE_FRD/WRITE_RD, which in turn gets passed // in from sv_insn_t::fimap... - sv_reg_entry *r; - if (intreg) - { - r = &sv_int_tb[reg]; - } - else - { - r = &sv_fp_tb[reg]; - } + sv_reg_entry *r = get_regentry(reg, intreg); + // next we check if this entry is active. if not, the register // is not being "redirected", so just return the actual reg. if (!r->active) @@ -111,18 +130,9 @@ uint64_t sv_insn_t::remap(uint64_t reg, bool intreg, int &voffs) * down to the number of bits in the predication i.e. the bitwidth of integer * registers (i.e. XLEN bits). */ -reg_t sv_insn_t::predicate(processor_t *p, uint64_t reg, - bool intreg, bool &zeroing) +reg_t sv_insn_t::predicate(uint64_t reg, bool intreg, bool &zeroing) { - sv_pred_entry *r; - if (intreg) - { - r = &sv_pred_int_tb[reg]; - } - else - { - r = &sv_pred_fp_tb[reg]; - } + sv_pred_entry *r = get_predentry(reg, intreg); if (!r->active) { return ~0x0; // not active: return all-1s (unconditional "on") diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h index 967c23a..727cf77 100644 --- a/riscv/sv_decode.h +++ b/riscv/sv_decode.h @@ -15,8 +15,8 @@ class sv_insn_t: public insn_t { public: - sv_insn_t(insn_bits_t bits, unsigned int f) : - insn_t(bits), fimap(f), + sv_insn_t(processor_t *pr, insn_bits_t bits, unsigned int f) : + insn_t(bits), p(pr), fimap(f), cached_rd(0xff), cached_rs1(0xff), cached_rs2(0xff), cached_rs3(0xff), offs_rd(0), offs_rs1(0), @@ -37,9 +37,14 @@ public: cached_rs2 = 0xff; cached_rs3 = 0xff; } - reg_t predicate(processor_t* p, uint64_t reg, bool isint, bool &zeroing); + + bool sv_check_reg(bool intreg, uint64_t reg); + sv_reg_entry* get_regentry(uint64_t reg, bool isint); + sv_pred_entry* get_predentry(uint64_t reg, bool isint); + reg_t predicate(uint64_t reg, bool isint, bool &zeroing); private: + processor_t *p; unsigned int fimap; uint64_t cached_rd; uint64_t cached_rs1; -- 2.30.2