From d4488748799613738de99f5948bf700678c9897c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 23 Jan 2018 10:28:16 +0100 Subject: [PATCH] sim: rename top module to dut and use --top-module parameter (needed for picorv32 simulation) --- litex/build/sim/core/Makefile | 2 +- litex/build/sim/verilator.py | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/litex/build/sim/core/Makefile b/litex/build/sim/core/Makefile index 0388cdda..782ac46b 100644 --- a/litex/build/sim/core/Makefile +++ b/litex/build/sim/core/Makefile @@ -24,7 +24,7 @@ $(OBJS_SIM): %.o: $(SRC_DIR)/%.c .PHONY: sim sim: mkdir $(OBJS_SIM) - verilator -Wno-fatal -O3 --cc dut.v --exe \ + verilator -Wno-fatal -O3 --cc dut.v --top-module dut --exe \ $(SRCS_SIM_CPP) $(OBJS_SIM) \ -CFLAGS "$(CFLAGS) -I$(SRC_DIR)" \ -LDFLAGS "$(LDFLAGS)" \ diff --git a/litex/build/sim/verilator.py b/litex/build/sim/verilator.py index 312d51e3..a2e39b47 100644 --- a/litex/build/sim/verilator.py +++ b/litex/build/sim/verilator.py @@ -136,7 +136,7 @@ sudo obj_dir/Vdut class SimVerilatorToolchain: - def build(self, platform, fragment, build_dir="build", build_name="top", + def build(self, platform, fragment, build_dir="build", build_name="dut", toolchain_path=None, serial="console", run=True, verbose=True, sim_config=None): os.makedirs(build_dir, exist_ok=True) @@ -146,9 +146,9 @@ class SimVerilatorToolchain: fragment = fragment.get_fragment() platform.finalize(fragment) - v_output = platform.get_verilog(fragment) + v_output = platform.get_verilog(fragment, name=build_name) named_sc, named_pc = platform.resolve_signals(v_output.ns) - v_output.write("dut.v") + v_output.write(build_name + ".v") include_paths = [] for source in platform.sources: -- 2.30.2