From d452d156988b859b790b560ea2f22beba824fb81 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 26 Sep 2020 16:08:45 +0100 Subject: [PATCH] add ls180io.py --- src/soc/litex/florent/libresoc/ls180io.py | 40 +++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 src/soc/litex/florent/libresoc/ls180io.py diff --git a/src/soc/litex/florent/libresoc/ls180io.py b/src/soc/litex/florent/libresoc/ls180io.py new file mode 100644 index 00000000..03d2cdc3 --- /dev/null +++ b/src/soc/litex/florent/libresoc/ls180io.py @@ -0,0 +1,40 @@ +# +# This file is part of LiteX. +# +# Copyright (c) 2018-2019 Florent Kermarrec +# SPDX-License-Identifier: BSD-2-Clause + +"""ls180 ASIC platform + +conceptually similar to the following: + +* https://github.com/enjoy-digital/liteeth/blob/master/liteeth/gen.py +* https://github.com/enjoy-digital/litepcie/blob/master/litepcie/gen.py + +Total I/O pins: 84. +Fits in a JEDEC QFP-100 + +""" + +from litex.build.generic_platform import (GenericPlatform, Pins, + Subsignal, IOStandard, Misc, + ) +import os + +def make_uart(name, num): + return (name, num, + Subsignal("tx", Pins("L4"), IOStandard("LVCMOS33")), + Subsignal("rx", Pins("M1"), IOStandard("LVCMOS33")) + ) + +def make_gpio(name, num, n_gpio): + pins = [] + for i in range(n_gpio): + pins.append("X%d" % i) + pins = ' '.join(pins) + return (name, 0, + Subsignal("i", Pins(pins), Misc("PULLMODE=UP")), + Subsignal("o", Pins(pins), Misc("PULLMODE=UP")), + Subsignal("oe", Pins(pins), Misc("PULLMODE=UP")), + IOStandard("LVCMOS33")) + -- 2.30.2