From d458b5845c80d526b6701671c52c63a62bceb30c Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Sat, 16 Oct 2021 19:24:14 +1100 Subject: [PATCH] ECP5: Adjust PLL constants so the PLL lock indication works At present, code (such as simple_random) which produces serial port output during the first few milliseconds of operation produces garbled output. The reason is that the clock has not yet stabilized and is running slow, resulting in the bit time of the serial characters being too long. The ECP5 data sheet says that the phase detector should be operated between 10 and 400 MHz. The current code operates it at 2MHz. Consequently, the PLL lock indication doesn't work, i.e. it is always zero. The current code works around that by inverting it, i.e. taking the "not locked" indication to mean "locked". Instead, we now run it at 12MHz, chosen because the common external clock inputs on ECP5 boards are 12MHz and 48MHz. Normally this would mean that the available system clock frequencies would be multiples of 12MHz, but this is a little inconvenient as we use 40MHz on the Orange Crab v0.21 boards. Instead, by using the secondary clock output for feedback, we can have any divisor of the PLL frequency as the system clock frequency. The ECP5 data sheet says the PLL oscillator can run at 400 to 800 MHz. Here we choose 480MHz since that allows us to generate 40MHz and 48MHz easily and is a multiple of 12MHz. With this, the lock signal works correctly, and the inversion can be removed. Signed-off-by: Paul Mackerras --- fpga/clk_gen_ecp5.vhd | 29 +++++++++++++++++++---------- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/fpga/clk_gen_ecp5.vhd b/fpga/clk_gen_ecp5.vhd index 7b0f40a..ffb3b06 100644 --- a/fpga/clk_gen_ecp5.vhd +++ b/fpga/clk_gen_ecp5.vhd @@ -82,33 +82,42 @@ architecture bypass of clock_generator is CLKINTFB : out std_logic ); end component; + signal clkos : std_ulogic; signal clkop : std_logic; signal lock : std_logic; - -- PLL constants based on prjtrellis example - constant PLL_IN : natural := 2000000; - constant PLL_OUT : natural := 600000000; + -- PLL constants + -- According to the datasheet, PLL_IN needs to be between 10 and 400 MHz + -- PLL_OUT needs to be between 400 and 800 MHz + -- PLL_IN is chosen based on 12 and 48 MHz being common values + -- for the reference clock. + constant PLL_IN : natural := 12000000; + constant PLL_OUT : natural := 480000000; -- Configration for ECP5 PLL constant PLL_CLKOP_DIV : natural := PLL_OUT/CLK_OUTPUT_HZ; - constant PLL_CLKFB_DIV : natural := CLK_OUTPUT_HZ/PLL_IN; + constant PLL_CLKOS_DIV : natural := 2; + constant PLL_CLKFB_DIV : natural := PLL_OUT/PLL_CLKOS_DIV/PLL_IN; constant PLL_CLKI_DIV : natural := CLK_INPUT_HZ/PLL_IN; begin pll_clk_out <= clkop; - pll_locked_out <= not lock; -- FIXME: EHXPLLL lock signal active low?!? + pll_locked_out <= lock; clkgen: EHXPLLL generic map( - CLKOP_CPHASE => 11, -- FIXME: Copied from prjtrells. CLKOP_DIV => PLL_CLKOP_DIV, + CLKOS_ENABLE => "ENABLED", + CLKOS_DIV => PLL_CLKOS_DIV, CLKFB_DIV => PLL_CLKFB_DIV, - CLKI_DIV => PLL_CLKI_DIV + CLKI_DIV => PLL_CLKI_DIV, + FEEDBK_PATH => "CLKOS" ) port map ( CLKI => ext_clk, CLKOP => clkop, - CLKFB => clkop, + CLKOS => clkos, + CLKFB => clkos, LOCK => lock, RST => pll_rst_in, PHASESEL1 => '0', @@ -118,8 +127,8 @@ begin PHASELOADREG => '0', STDBY => '0', PLLWAKESYNC => '0', - ENCLKOP => '0', - ENCLKOS => '0', + ENCLKOP => '1', + ENCLKOS => '1', ENCLKOS2 => '0', ENCLKOS3 => '0' ); -- 2.30.2