From d46fb2126d9fdd52386b001a140c1b70fec83f9e Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Sun, 6 Mar 2016 18:13:59 -0800 Subject: [PATCH] intel/compiler: Move base IR definitions into a separate header file This pulls out the i965 IR definitions into a separate file and leaves the top-level backend_shader structure and back-end compiler entry points in brw_shader.h. The purpose is to keep things tidy and prevent a nasty circular dependency between brw_cfg.h and brw_shader.h. The logical dependency between these data structures looks like: backend_shader (brw_shader.h) -> cfg_t (brw_cfg.h) -> bblock_t (brw_cfg.h) -> backend_instruction (brw_shader.h) This circular header dependency is currently resolved by using forward declarations of cfg_t/bblock_t in brw_shader.h and having brw_cfg.h include brw_shader.h, which seems backwards and won't work at all when the forward declarations of cfg_t/bblock_t are no longer sufficient in a future commit. Reviewed-by: Matt Turner Part-of: --- src/intel/compiler/brw_ir.h | 181 ++++++++++++++++++++++++++++++++ src/intel/compiler/brw_shader.h | 159 +--------------------------- src/intel/compiler/meson.build | 1 + 3 files changed, 184 insertions(+), 157 deletions(-) create mode 100644 src/intel/compiler/brw_ir.h diff --git a/src/intel/compiler/brw_ir.h b/src/intel/compiler/brw_ir.h new file mode 100644 index 00000000000..c2c4893b3f6 --- /dev/null +++ b/src/intel/compiler/brw_ir.h @@ -0,0 +1,181 @@ +/* -*- c++ -*- */ +/* + * Copyright © 2010-2016 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#ifndef BRW_IR_H +#define BRW_IR_H + +#include +#include "brw_reg.h" +#include "compiler/glsl/list.h" + +#define MAX_SAMPLER_MESSAGE_SIZE 11 +#define MAX_VGRF_SIZE 16 + +#ifdef __cplusplus +struct backend_reg : private brw_reg +{ + backend_reg() {} + backend_reg(const struct brw_reg ®) : brw_reg(reg) {} + + const brw_reg &as_brw_reg() const + { + assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM); + assert(offset == 0); + return static_cast(*this); + } + + brw_reg &as_brw_reg() + { + assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM); + assert(offset == 0); + return static_cast(*this); + } + + bool equals(const backend_reg &r) const; + bool negative_equals(const backend_reg &r) const; + + bool is_zero() const; + bool is_one() const; + bool is_negative_one() const; + bool is_null() const; + bool is_accumulator() const; + + /** Offset from the start of the (virtual) register in bytes. */ + uint16_t offset; + + using brw_reg::type; + using brw_reg::file; + using brw_reg::negate; + using brw_reg::abs; + using brw_reg::address_mode; + using brw_reg::subnr; + using brw_reg::nr; + + using brw_reg::swizzle; + using brw_reg::writemask; + using brw_reg::indirect_offset; + using brw_reg::vstride; + using brw_reg::width; + using brw_reg::hstride; + + using brw_reg::df; + using brw_reg::f; + using brw_reg::d; + using brw_reg::ud; + using brw_reg::d64; + using brw_reg::u64; +}; + +struct bblock_t; + +struct backend_instruction : public exec_node { + bool is_3src(const struct gen_device_info *devinfo) const; + bool is_tex() const; + bool is_math() const; + bool is_control_flow() const; + bool is_commutative() const; + bool can_do_source_mods() const; + bool can_do_saturate() const; + bool can_do_cmod() const; + bool reads_accumulator_implicitly() const; + bool writes_accumulator_implicitly(const struct gen_device_info *devinfo) const; + + void remove(bblock_t *block); + void insert_after(bblock_t *block, backend_instruction *inst); + void insert_before(bblock_t *block, backend_instruction *inst); + void insert_before(bblock_t *block, exec_list *list); + + /** + * True if the instruction has side effects other than writing to + * its destination registers. You are expected not to reorder or + * optimize these out unless you know what you are doing. + */ + bool has_side_effects() const; + + /** + * True if the instruction might be affected by side effects of other + * instructions. + */ + bool is_volatile() const; +#else +struct backend_instruction { + struct exec_node link; +#endif + /** @{ + * Annotation for the generated IR. One of the two can be set. + */ + const void *ir; + const char *annotation; + /** @} */ + + /** + * Execution size of the instruction. This is used by the generator to + * generate the correct binary for the given instruction. Current valid + * values are 1, 4, 8, 16, 32. + */ + uint8_t exec_size; + + /** + * Channel group from the hardware execution and predication mask that + * should be applied to the instruction. The subset of channel enable + * signals (calculated from the EU control flow and predication state) + * given by [group, group + exec_size) will be used to mask GRF writes and + * any other side effects of the instruction. + */ + uint8_t group; + + uint32_t offset; /**< spill/unspill offset or texture offset bitfield */ + uint8_t mlen; /**< SEND message length */ + uint8_t ex_mlen; /**< SENDS extended message length */ + int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */ + uint8_t target; /**< MRT target. */ + uint8_t sfid; /**< SFID for SEND instructions */ + uint32_t desc; /**< SEND[S] message descriptor immediate */ + unsigned size_written; /**< Data written to the destination register in bytes. */ + + enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */ + enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */ + enum brw_predicate predicate; + bool predicate_inverse:1; + bool writes_accumulator:1; /**< instruction implicitly writes accumulator */ + bool force_writemask_all:1; + bool no_dd_clear:1; + bool no_dd_check:1; + bool saturate:1; + bool shadow_compare:1; + bool check_tdr:1; /**< Only valid for SEND; turns it into a SENDC */ + bool send_has_side_effects:1; /**< Only valid for SHADER_OPCODE_SEND */ + bool send_is_volatile:1; /**< Only valid for SHADER_OPCODE_SEND */ + bool eot:1; + + /* Chooses which flag subregister (f0.0 to f1.1) is used for conditional + * mod and predication. + */ + unsigned flag_subreg:2; + + /** The number of hardware registers used for a message header. */ + uint8_t header_size; +}; + +#endif diff --git a/src/intel/compiler/brw_shader.h b/src/intel/compiler/brw_shader.h index 61b5cd6fad3..ebf6c2f3674 100644 --- a/src/intel/compiler/brw_shader.h +++ b/src/intel/compiler/brw_shader.h @@ -25,169 +25,14 @@ #define BRW_SHADER_H #include -#include "brw_reg.h" +#include "brw_ir.h" #include "brw_compiler.h" -#include "brw_eu_defines.h" -#include "brw_inst.h" #include "compiler/nir/nir.h" -#ifdef __cplusplus -#include "brw_ir_allocator.h" -#endif - -#define MAX_SAMPLER_MESSAGE_SIZE 11 -#define MAX_VGRF_SIZE 16 - -#ifdef __cplusplus -struct backend_reg : private brw_reg -{ - backend_reg() {} - backend_reg(const struct brw_reg ®) : brw_reg(reg) {} - - const brw_reg &as_brw_reg() const - { - assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM); - assert(offset == 0); - return static_cast(*this); - } - - brw_reg &as_brw_reg() - { - assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM); - assert(offset == 0); - return static_cast(*this); - } - - bool equals(const backend_reg &r) const; - bool negative_equals(const backend_reg &r) const; - - bool is_zero() const; - bool is_one() const; - bool is_negative_one() const; - bool is_null() const; - bool is_accumulator() const; - - /** Offset from the start of the (virtual) register in bytes. */ - uint16_t offset; - - using brw_reg::type; - using brw_reg::file; - using brw_reg::negate; - using brw_reg::abs; - using brw_reg::address_mode; - using brw_reg::subnr; - using brw_reg::nr; - - using brw_reg::swizzle; - using brw_reg::writemask; - using brw_reg::indirect_offset; - using brw_reg::vstride; - using brw_reg::width; - using brw_reg::hstride; - - using brw_reg::df; - using brw_reg::f; - using brw_reg::d; - using brw_reg::ud; - using brw_reg::d64; - using brw_reg::u64; -}; -#endif - struct cfg_t; -struct bblock_t; - -#ifdef __cplusplus -struct backend_instruction : public exec_node { - bool is_3src(const struct gen_device_info *devinfo) const; - bool is_tex() const; - bool is_math() const; - bool is_control_flow() const; - bool is_commutative() const; - bool can_do_source_mods() const; - bool can_do_saturate() const; - bool can_do_cmod() const; - bool reads_accumulator_implicitly() const; - bool writes_accumulator_implicitly(const struct gen_device_info *devinfo) const; - - void remove(bblock_t *block); - void insert_after(bblock_t *block, backend_instruction *inst); - void insert_before(bblock_t *block, backend_instruction *inst); - void insert_before(bblock_t *block, exec_list *list); - - /** - * True if the instruction has side effects other than writing to - * its destination registers. You are expected not to reorder or - * optimize these out unless you know what you are doing. - */ - bool has_side_effects() const; - - /** - * True if the instruction might be affected by side effects of other - * instructions. - */ - bool is_volatile() const; -#else -struct backend_instruction { - struct exec_node link; -#endif - /** @{ - * Annotation for the generated IR. One of the two can be set. - */ - const void *ir; - const char *annotation; - /** @} */ - - /** - * Execution size of the instruction. This is used by the generator to - * generate the correct binary for the given instruction. Current valid - * values are 1, 4, 8, 16, 32. - */ - uint8_t exec_size; - - /** - * Channel group from the hardware execution and predication mask that - * should be applied to the instruction. The subset of channel enable - * signals (calculated from the EU control flow and predication state) - * given by [group, group + exec_size) will be used to mask GRF writes and - * any other side effects of the instruction. - */ - uint8_t group; - - uint32_t offset; /**< spill/unspill offset or texture offset bitfield */ - uint8_t mlen; /**< SEND message length */ - uint8_t ex_mlen; /**< SENDS extended message length */ - int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */ - uint8_t target; /**< MRT target. */ - uint8_t sfid; /**< SFID for SEND instructions */ - uint32_t desc; /**< SEND[S] message descriptor immediate */ - unsigned size_written; /**< Data written to the destination register in bytes. */ - - enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */ - enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */ - enum brw_predicate predicate; - bool predicate_inverse:1; - bool writes_accumulator:1; /**< instruction implicitly writes accumulator */ - bool force_writemask_all:1; - bool no_dd_clear:1; - bool no_dd_check:1; - bool saturate:1; - bool shadow_compare:1; - bool check_tdr:1; /**< Only valid for SEND; turns it into a SENDC */ - bool send_has_side_effects:1; /**< Only valid for SHADER_OPCODE_SEND */ - bool send_is_volatile:1; /**< Only valid for SHADER_OPCODE_SEND */ - bool eot:1; - - /* Chooses which flag subregister (f0.0 to f1.1) is used for conditional - * mod and predication. - */ - unsigned flag_subreg:2; - - /** The number of hardware registers used for a message header. */ - uint8_t header_size; -}; #ifdef __cplusplus +#include "brw_ir_allocator.h" enum instruction_scheduler_mode { SCHEDULE_PRE, diff --git a/src/intel/compiler/meson.build b/src/intel/compiler/meson.build index 4a4a76cece8..2c44949c2b7 100644 --- a/src/intel/compiler/meson.build +++ b/src/intel/compiler/meson.build @@ -68,6 +68,7 @@ libintel_compiler_files = files( 'brw_fs_visitor.cpp', 'brw_inst.h', 'brw_interpolation_map.c', + 'brw_ir.h', 'brw_ir_allocator.h', 'brw_ir_fs.h', 'brw_ir_vec4.h', -- 2.30.2