From d49f0192f06d9df5ef5dbeb8fcefc7806409c729 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 2 Mar 2021 12:49:18 +0000 Subject: [PATCH] must always set ok for writing out data otherwise it never hits regfile (and causes compunit to fail) --- src/soc/fu/mmu/fsm.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py index c2e82f4a..0b3b728e 100644 --- a/src/soc/fu/mmu/fsm.py +++ b/src/soc/fu/mmu/fsm.py @@ -257,7 +257,7 @@ class FSMMMUStage(ControlBase): comb += o.data.eq(dsisr) with m.Else(): comb += o.data.eq(dar) - #FIXME comb += o.ok.eq(1) + comb += o.ok.eq(1) comb += done.eq(1) # pass it over to the MMU instead with m.Else(): -- 2.30.2