From d4baac6c0f8241c6807632d62e9e13709141758c Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 17 Nov 2012 19:44:25 +0100 Subject: [PATCH] bus/csr: allow specifying existing interface --- migen/bus/csr.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/migen/bus/csr.py b/migen/bus/csr.py index 0bce395d..df254348 100644 --- a/migen/bus/csr.py +++ b/migen/bus/csr.py @@ -17,9 +17,9 @@ class Interconnect(SimpleInterconnect): pass class Initiator(PureSimulable): - def __init__(self, generator): + def __init__(self, generator, bus=Interface()): self.generator = generator - self.bus = Interface() + self.bus = bus self.transaction = None self.done = False -- 2.30.2