From d4d125bce97d57504eee707a359ae1d34e171494 Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 11 Apr 2022 03:12:58 +0100 Subject: [PATCH] --- openpower/sv/svp64/appendix.mdwn | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn index 585374731..d04d66de7 100644 --- a/openpower/sv/svp64/appendix.mdwn +++ b/openpower/sv/svp64/appendix.mdwn @@ -548,13 +548,11 @@ is performed, and if it fails it is considered to have been *as if* the destination predicate bit was zero. Arithmetic and Logical Pred-result is covered in [[sv/normal]] -## pred-result mode on CR ops +Ped-result mode may not be applied on CR ops. -CR operations (mtcr, crand, cror) may be Vectorised, -predicated, and also pred-result mode applied to it. -Vectorisation applies to 4-bit CR Fields which are treated as -elements, not the individual bits of the 32-bit CR. -CR ops and how to identify them is described in [[sv/cr_ops]] +Although CR operations (mtcr, crand, cror) may be Vectorised, +predicated, pred-result mode applies to operations that have +an Rc=1 mode, or make sense to add an RC1 option. # CR Operations -- 2.30.2