From d4daf3685be056a6b45ce5365e0a8c076d009a04 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 8 Oct 2022 14:28:00 +0100 Subject: [PATCH] add sc and scv support after moving from major.csv to extra.csv this now involves a laborious brute-force search looking for anything with an extra.csv path, in order to prioritise the (full) 32-bit pattern-match over e.g. MAJOR XO=17. attn should also work (but currently does not, no idea why, possibly because it should actually be in major.csv? --- openpower/isatables/extra.csv | 2 + openpower/isatables/major.csv | 1 - src/openpower/decoder/power_insn.py | 19 ++++++- src/openpower/sv/trans/test_pysvp64dis.py | 68 +++++++++++++---------- 4 files changed, 59 insertions(+), 31 deletions(-) diff --git a/openpower/isatables/extra.csv b/openpower/isatables/extra.csv index ce090cb3..4ce39a02 100644 --- a/openpower/isatables/extra.csv +++ b/openpower/isatables/extra.csv @@ -2,3 +2,5 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou 000000---------------0100000000-,NONE,OP_ATTN,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,1,attn,NONE,,0,"service processor ""attention""" 01100000000000000000000000000000,NONE,OP_NOP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,nop,D,,0, 000001---------------0000000011-,NONE,OP_SIM_CONFIG,NONE,NONE,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,sim_cfg,NONE,,1,should be removed--conflicts with ISA v3.1 prefix and SVP64 prefix +010001------------------------1-,TRAP,OP_SC,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,sc,SC, +010001------------------------01,TRAP,OP_SC,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,scv,SC, diff --git a/openpower/isatables/major.csv b/openpower/isatables/major.csv index a091f45c..318b7852 100644 --- a/openpower/isatables/major.csv +++ b/openpower/isatables/major.csv @@ -3,7 +3,6 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou 13,ALU,OP_ADD,RA,CONST_SI,NONE,RT,NONE,CR0,0,0,ZERO,1,NONE,0,0,0,0,0,0,ONE,0,0,addic.,D, 14,ALU,OP_ADD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,addi,D, 15,ALU,OP_ADD,RA_OR_ZERO,CONST_SI_HI,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,addis,D, -17,TRAP,OP_SC,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,sc,SC, 28,LOGICAL,OP_AND,RS,CONST_UI,NONE,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,ONE,0,0,andi.,D, 29,LOGICAL,OP_AND,RS,CONST_UI_HI,NONE,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,ONE,0,0,andis.,D, 18,BRANCH,OP_B,NONE,CONST_LI,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,1,0,b,I, diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py index 26fc7591..65cbb242 100644 --- a/src/openpower/decoder/power_insn.py +++ b/src/openpower/decoder/power_insn.py @@ -2185,6 +2185,8 @@ class PPCDatabase: for name in insn.names: records[name].add(insn) sections[name] = section + if str(path).endswith("extra.csv"): + print ("extra", name, section) for (name, multirecord) in sorted(records.items()): multirecord = PPCMultiRecord(sorted(multirecord)) @@ -2316,6 +2318,9 @@ class Database: self.__db = sorted(db) self.__names = dict(sorted(names.items())) self.__opcodes = dict(sorted(opcodes.items())) + print ("opcodes") + for k, v in self.__opcodes.items(): + print (" ", bin(k), v) return super().__init__() @@ -2331,13 +2336,25 @@ class Database: @_functools.lru_cache(maxsize=None) def __getitem__(self, key): + # specific hunt for all "extra.csv" matches. TODO: separate db of extras + if isinstance(key, Instruction): + ki = int(key) + print ("key", bin(ki)) + for k, records in self.__opcodes.items(): + for record in records: + if str(record.section.path).endswith("extra.csv"): + if record.match(key=ki): + return record + # now look by XO-match, first, which is much better sorted. + # not in major.csv (e.g. 17 which is in extra.csv) already done above if isinstance(key, (int, Instruction)): key = int(key) XO = int(_SelectableInt(value=int(key), bits=32)[0:6]) + assert XO in self.__opcodes # should have been caught by extra.csv for record in self.__opcodes[XO]: if record.match(key=key): return record - + # hunt by string instead elif isinstance(key, str): return self.__names[key] diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py index 506a0673..cd70473b 100644 --- a/src/openpower/sv/trans/test_pysvp64dis.py +++ b/src/openpower/sv/trans/test_pysvp64dis.py @@ -30,7 +30,7 @@ class SVSTATETestCase(unittest.TestCase): "'%s' expected '%s'" % (line, expected[i])) - def test_0_add(self): + def tst_0_add(self): expected = ['addi 1,5,2', 'add 1,5,2', 'add. 1,5,2', @@ -39,13 +39,13 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) - def test_1_svshape2(self): + def tst_1_svshape2(self): expected = [ 'svshape2 12,1,15,5,0,0' ] self._do_tst(expected) - def test_2_d_custom_op(self): + def tst_2_d_custom_op(self): expected = [ 'fishmv 12,2', 'fmvis 12,97', @@ -53,7 +53,7 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) - def test_3_sv_isel(self): + def tst_3_sv_isel(self): expected = [ 'sv.isel 12,2,3,33', 'sv.isel 12,2,3,*33', @@ -63,7 +63,7 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) - def test_4_sv_crand(self): + def tst_4_sv_crand(self): expected = [ 'sv.crand *16,*2,*33', 'sv.crand 12,2,33', @@ -76,21 +76,21 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) - def test_5_setvl(self): + def tst_5_setvl(self): expected = [ "setvl 5,4,5,0,1,1", "setvl. 5,4,5,0,1,1", ] self._do_tst(expected) - def test_6_sv_setvl(self): + def tst_6_sv_setvl(self): expected = [ "sv.setvl 5,4,5,0,1,1", "sv.setvl 63,35,5,0,1,1", ] self._do_tst(expected) - def test_7_batch(self): + def tst_7_batch(self): "these come from https://bugs.libre-soc.org/show_bug.cgi?id=917#c25" expected = [ "addi 2,2,0", @@ -164,7 +164,7 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) - def test_8_madd(self): + def tst_8_madd(self): expected = [ "maddhd 5,4,5,3", "maddhdu 5,4,5,3", @@ -172,14 +172,14 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) - def test_9_fptrans(self): + def tst_9_fptrans(self): "enumerates a list of fptrans instruction disassembly entries" db = Database(find_wiki_dir()) entries = sorted(sv_binutils_fptrans.collect(db)) dis = lambda entry: sv_binutils_fptrans.dis(entry, binutils=False) self._do_tst(list(map(dis, entries))) - def test_10_vec(self): + def tst_10_vec(self): expected = [ "sv.add./vec2 *3,*7,*11", "sv.add./vec3 *3,*7,*11", @@ -187,7 +187,7 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) - def test_11_elwidth(self): + def tst_11_elwidth(self): expected = [ "sv.add./dw=8 *3,*7,*11", "sv.add./dw=16 *3,*7,*11", @@ -204,14 +204,14 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) - def test_12_sat(self): + def tst_12_sat(self): expected = [ "sv.add./satu *3,*7,*11", "sv.add./sats *3,*7,*11", ] self._do_tst(expected) - def test_12_mr_r(self): + def tst_12_mr_r(self): expected = [ "sv.add./mrr/vec2 *3,*7,*11", "sv.add./mr/vec2 *3,*7,*11", @@ -220,7 +220,7 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) - def test_13_RC1(self): + def tst_13_RC1(self): expected = [ "sv.add/ff=RC1 *3,*7,*11", "sv.add/pr=RC1 *3,*7,*11", @@ -229,7 +229,7 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) - def test_14_rc1_ff_pr(self): + def tst_14_rc1_ff_pr(self): expected = [ "sv.add./ff=eq *3,*7,*11", "sv.add./ff=ns *3,*7,*11", @@ -243,7 +243,7 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) - def test_15_predicates(self): + def tst_15_predicates(self): expected = [ "sv.add./m=r3 *3,*7,*11", "sv.add./m=1<