From d4ead2f28017f52d565a33ee6d45eeaefc521f91 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 9 Apr 2022 23:06:09 +0100
Subject: [PATCH] add QSPI dump back in (smaller one) to check it is working

---
 coldboot/coldboot.c | 48 +++++++++++++++++++++++----------------------
 src/ls2.py          |  2 +-
 2 files changed, 26 insertions(+), 24 deletions(-)

diff --git a/coldboot/coldboot.c b/coldboot/coldboot.c
index 020d9dc..0f42a82 100644
--- a/coldboot/coldboot.c
+++ b/coldboot/coldboot.c
@@ -190,36 +190,38 @@ int main(void) {
 
 #endif
 
-#if 0
+#if 1
 #if 1
     // print out configuration parameters for QSPI
-	volatile uint32_t *qspi_cfg = (uint32_t*)0xc0003000;
+	volatile uint32_t *qspi_cfg = (uint32_t*)SPI_FCTRL_BASE;
     for (int k=0; k < 2; k++) {
         tmp = readl((unsigned long)&(qspi_cfg[k]));
-        //puts("cfg");
-        //uart_writeuint32(k);
-        //puts(" ");
-        //uart_writeuint32(tmp);
-        //puts("\n");
+        puts("cfg");
+        uart_writeuint32(k);
+        puts(" ");
+        uart_writeuint32(tmp);
+        puts("\n");
     }
 #endif
-	volatile uint32_t *qspi = (uint32_t*)spi_mem;
-       volatile uint8_t *qspi_bytes = (uint8_t*)spi_mem;
+	volatile uint32_t *qspi = (uint32_t*)spi_offs;
+    //volatile uint8_t *qspi_bytes = (uint8_t*)spi_offs;
      // let's not, eh? writel(0xDEAF0123, (unsigned long)&(qspi[0]));
      // tmp = readl((unsigned long)&(qspi[0]));
-for (i=0;i<1000;i++) {
-  tmp = readl((unsigned long)&(qspi[i]));
-  uart_writeuint32(tmp);
-  puts(" ");
-}
-putchar(10);
-putchar(10);
-for (i=0;i<1000;i++) {
-  tmp = readb((unsigned long)&(qspi_bytes[i]));
-  uart_writeuint32(tmp);
-  puts(" ");
-}
-#if 1
+    for (int i=0;i<256;i++) {
+      tmp = readl((unsigned long)&(qspi[i]));
+      uart_writeuint32(tmp);
+      puts(" ");
+      if ((i & 0x7) == 0x7) puts("\r\n");
+    }
+    puts("\r\n");
+    /*
+    for (i=0;i<256;i++) {
+      tmp = readb((unsigned long)&(qspi_bytes[i]));
+      uart_writeuint32(tmp);
+      puts(" ");
+    }
+    */
+#if 0
     while (1) {
         // quick read
         tmp = readl((unsigned long)&(qspi[0x1000/4]));
@@ -227,7 +229,6 @@ for (i=0;i<1000;i++) {
         uart_writeuint32(tmp);
         putchar(10);
     }
-#endif
     while (1) {
         unsigned char c = getchar();
         putchar(c);
@@ -246,6 +247,7 @@ for (i=0;i<1000;i++) {
 
     return 0;
 #endif
+#endif
 #if 0
 	volatile uint32_t *hyperram = (uint32_t*)0xa0000000;
     writel(0xDEAF0123, (unsigned long)&(hyperram[0]));
diff --git a/src/ls2.py b/src/ls2.py
index 6cd644f..3909b8a 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -818,7 +818,7 @@ def build_platform(fpga, firmware):
                   dramcore_addr=0xc8000000, # DRAM_CTRL_BASE
                   ddr_addr=0x00000000,      # DRAM_BASE
                   spi0_addr=0xf0000000,     # SPI0_BASE
-                  spi0_cfg_addr=0xc0003000, # SPI0_CTRL_BASE
+                  spi0_cfg_addr=0xc0006000, # SPI0_CTRL_BASE
                   eth0_cfg_addr=0xc0004000, # ETH0_CTRL_BASE (4k)
                   eth0_irqno=0,             # ETH0_IRQ number
                   hyperram_addr=0xa0000000, # HYPERRAM_BASE
-- 
2.30.2