From d51fc2dc33c3f2b521e7fe6efde1154597aec76b Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 23 Oct 2021 19:57:59 +0100 Subject: [PATCH] --- 3d_gpu/architecture/dynamic_simd/slice.mdwn | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/3d_gpu/architecture/dynamic_simd/slice.mdwn b/3d_gpu/architecture/dynamic_simd/slice.mdwn index c185e6404..2fac03f39 100644 --- a/3d_gpu/architecture/dynamic_simd/slice.mdwn +++ b/3d_gpu/architecture/dynamic_simd/slice.mdwn @@ -202,9 +202,17 @@ obviously so) and consequently b needs expanding to the same padding and PartitionPoints: elwid | | | | | | | - 0b00 x x x x x x x x x x x x x x B1B0 - 0b01 x x x x x x B5B4 x x x x x x B1B0 - 0b10 x x B7B6 x x B5B4 x x B3B2 x x B1B0 + 0b00 x x x x x x x x x x x x x 0 B1B0 + 0b01 x x x x x 0 B5B4 x 0 x x x 0 B1B0 + 0b10 x 0 B7B6 x 0 B5B4 x 0 B3B2 x 0 B1B0 + +Note here that zero-extension also had to occur to +bring b up to the same element width in each partition, +at which point, "x" padding being ignored, a straight +PartitionedAdd may be deployed because both the overall +width and the positions of the PartitionPoints are exactly +matched. + Illustrating the case where a Sliced (fixed element width) SimdSignal is added to one which has variable-length elements that take up the -- 2.30.2