From d52cd81f6f749574831c6be217ebec5a92f729da Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 6 Oct 2020 18:09:48 +0100 Subject: [PATCH] add ports function to DummyPLL --- src/soc/clock/select.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/clock/select.py b/src/soc/clock/select.py index 463852cf..23286b7a 100644 --- a/src/soc/clock/select.py +++ b/src/soc/clock/select.py @@ -88,6 +88,9 @@ class DummyPLL(Elaboratable): return m + def ports(self): + return [self.clk_24_i, self.clk_pll_o] + if __name__ == '__main__': dut = ClockSelect() -- 2.30.2