From d52f48c259a58d060dfdf28de464fbdf22fd0609 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 4 Jun 2020 21:00:58 +0100 Subject: [PATCH] add branch test case to core --- src/soc/simple/test/test_core.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py index 713da17d..6c8e0cd4 100644 --- a/src/soc/simple/test/test_core.py +++ b/src/soc/simple/test/test_core.py @@ -18,6 +18,7 @@ from soc.fu.alu.test.test_pipe_caller import ALUTestCase from soc.fu.logical.test.test_pipe_caller import LogicalTestCase from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase from soc.fu.cr.test.test_pipe_caller import CRTestCase +from soc.fu.branch.test.test_pipe_caller import BranchTestCase def set_cu_input(cu, idx, data): @@ -156,7 +157,7 @@ class TestRunner(FHDLTestCase): cr = test.cr print ("cr reg", hex(cr)) for i in range(8): - cri = (cr>>(j*4)) & 0xf + cri = (cr>>(i*4)) & 0xf print ("cr reg", hex(cri), i, core.regs.cr.regs[i].reg.shape()) yield core.regs.cr.regs[i].reg.eq(cri) @@ -233,6 +234,7 @@ if __name__ == "__main__": suite.addTest(TestRunner(ShiftRotTestCase.test_data)) suite.addTest(TestRunner(LogicalTestCase.test_data)) suite.addTest(TestRunner(ALUTestCase.test_data)) + suite.addTest(TestRunner(BranchTestCase.test_data)) runner = unittest.TextTestRunner() runner.run(suite) -- 2.30.2