From d54c4235c5945ed99ad99cdc24209d52733026af Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 7 May 2022 12:27:57 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index 47d012092..a93d29390 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -234,6 +234,12 @@ of magnitude increase in the number of hand-written lines of assembler compared to a well-designed Cray-style Vector ISA with a `setvl` instruction. +*Packed SIMD looped algorithms actually have to +contain multiple implementations processing fragments of data at +different SIMD widths: Cray-style Vectors have one, covering not +just current architectural implementations but future ones with +wider back-end ALUs as well.* + Assuming then that variable-length Vectors are obviously desirable, it becomes a matter of how, not if. Both Cray and NEC SX Aurora went the way of adding explicit Vector opcodes, a style which RVV -- 2.30.2