From d550ef0bf6d072706ae7d03468ade5b7c267cb6b Mon Sep 17 00:00:00 2001 From: David Edelsohn Date: Fri, 17 Mar 2006 16:45:46 +0000 Subject: [PATCH] pr26350.c: New. * gcc.target/powerpc/pr26350.c: New. * gcc.target/powerpc/indexed-addr.c: New. From-SVN: r112176 --- gcc/testsuite/ChangeLog | 5 ++++ .../gcc.target/powerpc/indexed-addr.c | 14 +++++++++ gcc/testsuite/gcc.target/powerpc/pr26350.c | 29 +++++++++++++++++++ 3 files changed, 48 insertions(+) create mode 100644 gcc/testsuite/gcc.target/powerpc/indexed-addr.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr26350.c diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 63fa39dbf52..1dca3d2db0c 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2006-03-17 David Edelsohn + + * gcc.target/powerpc/pr26350.c: New. + * gcc.target/powerpc/indexed-addr.c: New. + 2006-03-16 Roger Sayle * gfortran.dg/dependency_13.f90: New test case. diff --git a/gcc/testsuite/gcc.target/powerpc/indexed-addr.c b/gcc/testsuite/gcc.target/powerpc/indexed-addr.c new file mode 100644 index 00000000000..6933b23e01a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/indexed-addr.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-options "-O2" } */ + +/* { dg-final { scan-assembler "3,\.*3,\.*4" } } + +/* Ensure that indexed address are output with base address in rA position + and index in rB position. */ + +char +do_one (char *base, unsigned long offset) +{ + return base[offset]; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/pr26350.c b/gcc/testsuite/gcc.target/powerpc/pr26350.c new file mode 100644 index 00000000000..6b4b20627ef --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr26350.c @@ -0,0 +1,29 @@ +/* { dg-do compile { target { powerpc*-*-darwin* powerpc*-*-aix* rs6000-*-* powerpc*-*-linux* } } } */ +/* { dg-options "-O2 -mlong-double-128 -fpic" } */ + +typedef int int32_t __attribute__ ((__mode__ (__SI__))); +typedef unsigned char uint8_t; +typedef unsigned int uint32_t; +typedef struct REGS REGS; +typedef union { uint32_t F; } FW; +typedef union { struct { FW L; } F; } DW; +typedef struct _PSW { + DW ia; +} PSW; +struct REGS { + PSW psw; + DW cr[16]; +}; +struct ebfp { + long double v; +}; + +void s390_convert_fix32_to_bfp_ext_reg (REGS *regs) +{ + struct ebfp op1; + int32_t op2; + ((regs))->psw.ia.F.L.F += (4); + if(!((regs)->cr[(0)].F.L.F & 0x00040000)) + op1.v = (long double)op2; + put_ebfp(&op1); +} -- 2.30.2