From d554a2349c71f3a13516b6f6c689c0a8e8ed6acf Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 6 May 2022 00:39:57 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index 1b72d8d69..727e2d9f6 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -321,7 +321,19 @@ a decade ago after the Packed SIMD variants were considered to be duplicates. With it being completely inappropriate to attempt to Vectorise a Packed SIMD ISA designed 20 years ago with no Predication of any kind, the Scalar ISA, a much better all-round candidate for Vectorisation is -left anaemic. Fortunately, with the ISA Working Group being willing +left anaemic. + +A particular key instruction that is missing is `MV.X` which is +illustrated as `GPR(dest) = GPR(GPR(src))`. This horrendously +expensive instruction is almost never added to a Scalar ISA but +is almost always added to a Vector one, it allows for arbitrary +remapping of elements within a Vector to positions specified +by another Vector. A typical Scalar ISA will use Memory to +achieve this task, but with Vector ISAs the Vector Register Files are +usually so enormous, and so far away from Memory, that it is easier and +more efficient, architecturally, to provide these Indexing instructions. + +Fortunately, with the ISA Working Group being willing to consider RFCs (Requests For Change) these omissions have the potential to be corrected. -- 2.30.2