From d55d0982e1bdcd4cbffcc700d7f72f7868e2e12d Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 23 Oct 2021 23:16:21 +0100 Subject: [PATCH] --- 3d_gpu/architecture/dynamic_simd/slice.mdwn | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/3d_gpu/architecture/dynamic_simd/slice.mdwn b/3d_gpu/architecture/dynamic_simd/slice.mdwn index 39bc222e4..aa4890cce 100644 --- a/3d_gpu/architecture/dynamic_simd/slice.mdwn +++ b/3d_gpu/architecture/dynamic_simd/slice.mdwn @@ -230,7 +230,13 @@ by noting that even the padding sections may be Cat()ed together. Illustrating the case where a Sliced (fixed element width) SimdSignal is added to one which has variable-length elements that take up the -entirety of the partition (overall fixed width): +entirety of the partition (overall fixed width). + +* For elwid=0b00, b is 1x 8bit +* for elwid=0b01, b is 2x 4bit +* for elwid=0b10, b is 4x 2bit + +Thus, the partition subdivisions are: elwid | | | 0b00 B7B6 B5B4 B3B2 B1B0 -- 2.30.2