From d56848055f9082717c5c7b0c103399718c49b0f7 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 27 Oct 2023 10:51:34 +0100
Subject: [PATCH] add pifpstoreshift.mdwn and pifploadshift.mdwn as copies of
 their non-shifted variants

---
 openpower/isa/pifploadshift.mdwn  | 116 ++++++++++++++++++++++++++++++
 openpower/isa/pifpstoreshift.mdwn | 114 +++++++++++++++++++++++++++++
 2 files changed, 230 insertions(+)
 create mode 100644 openpower/isa/pifploadshift.mdwn
 create mode 100644 openpower/isa/pifpstoreshift.mdwn

diff --git a/openpower/isa/pifploadshift.mdwn b/openpower/isa/pifploadshift.mdwn
new file mode 100644
index 00000000..d9de3315
--- /dev/null
+++ b/openpower/isa/pifploadshift.mdwn
@@ -0,0 +1,116 @@
+<!-- X Instructions here described in PowerISA Version 3.0 B Book 1 -->
+
+<!-- Section 4.6.1 Floating-point storage access instructions. P 140 - 143 -->
+
+# Load Floating-Point Single with Post-Update
+
+D-Form
+
+* lfsup FRT,D(RA)
+
+Pseudo-code:
+
+    EA <- (RA) + EXTS(D)
+    FRT <- DOUBLE(MEM(RA, 4))
+    RA <- EA
+
+Description:
+
+    Let the effective address (EA) be the sum (RA)+D.
+
+    The word in storage addressed by EA is interpreted as
+    a floating-point single-precision operand. This word is
+    converted to floating-point double format (see
+    page 138) and placed into register FRT.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
+Special Registers Altered:
+
+    None
+
+# Load Floating-Point Single with Post-Update Indexed
+
+X-Form
+
+* lfsupx FRT,RA,RB
+
+Pseudo-code:
+
+    EA <- (RA) + (RB)
+    FRT <- DOUBLE(MEM(RA, 4))
+    RA <- EA
+
+Description:
+
+    Let the effective address (EA) be the sum (RA)+(RB).
+
+    The word in storage addressed by EA is interpreted as
+    a floating-point single-precision operand. This word is
+    converted to floating-point double format (see
+    page 138) and placed into register FRT.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
+Special Registers Altered:
+
+    None
+
+# Load Floating-Point Double with Post-Update
+
+D-Form
+
+* lfdup FRT,D(RA)
+
+Pseudo-code:
+
+    EA <- (RA) + EXTS(D)
+    FRT <- MEM(RA, 8)
+    RA <- EA
+
+Description:
+
+    Let the effective address (EA) be the sum (RA)+D.
+
+    The doubleword in storage addressed by EA is loaded
+    into register FRT.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
+Special Registers Altered:
+
+    None
+
+# Load Floating-Point Double with Post-Update Indexed
+
+X-Form
+
+* lfduxp FRT,RA,RB
+
+Pseudo-code:
+
+    EA <- (RA) + (RB)
+    FRT <- MEM(RA, 8)
+    RA <- EA
+
+Description:
+
+    Let the effective address (EA) be the sum (RA)+(RB).
+
+    The doubleword in storage addressed by EA is loaded
+    into register FRT.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
+Special Registers Altered:
+
+    None
+
diff --git a/openpower/isa/pifpstoreshift.mdwn b/openpower/isa/pifpstoreshift.mdwn
new file mode 100644
index 00000000..46dd74fa
--- /dev/null
+++ b/openpower/isa/pifpstoreshift.mdwn
@@ -0,0 +1,114 @@
+<!-- X Instructions here described in PowerISA Version 3.0 B Book 1 -->
+
+<!-- Section 4.6.3 Floating-point store instructions. P 144 - 147 -->
+
+# Store Floating-Point Single with Update
+
+D-Form
+
+* stfsu FRS,D(RA)
+
+Pseudo-code:
+
+    EA <- (RA) + EXTS(D)
+    MEM(RA, 4)<- SINGLE( (FRS) )
+    RA <- EA
+
+Description:
+
+    Let the effective address (EA) be the sum (RA) +D.
+
+    The contents of register FRS are converted to single
+    format (see page 142) and stored into the word in stor-
+    age addressed by RA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
+Special Registers Altered:
+
+    None
+
+# Store Floating-Point Single with Update Indexed
+
+X-Form
+
+* stfsux FRS,RA,RB
+
+Pseudo-code:
+
+    EA <- (RA) + (RB)
+    MEM(RA, 4)<- SINGLE( (FRS) )
+    RA <- EA
+
+Description:
+
+    Let the effective address (EA) be the sum (RA) +(RB).
+
+    The contents of register FRS are converted to single
+    format (see page 142) and stored into the word in stor-
+    age addressed by RA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
+Special Registers Altered:
+
+    None
+
+# Store Floating-Point Double with Update
+
+D-Form
+
+* stfdu FRS,D(RA)
+
+Pseudo-code:
+
+    EA <- (RA) + EXTS(D)
+    MEM(RA, 8)<- (FRS)
+    RA <- EA
+
+Description:
+
+    Let the effective address (EA) be the sum (RA)+D.
+
+    The contents of register FRS are stored into the dou-
+    bleword in storage addressed by RA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
+Special Registers Altered:
+
+    None
+
+# Store Floating-Point Double with Update Indexed
+
+X-Form
+
+* stfdux FRS,RA,RB
+
+Pseudo-code:
+
+    EA <- (RA) + (RB)
+    MEM(RA, 8)<- (FRS)
+    RA <- EA
+
+Description:
+
+    Let the effective address (EA) be the sum (RA)+(RB).
+
+    The contents of register FRS are stored into the dou-
+    bleword in storage addressed by RA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
+Special Registers Altered:
+
+    None
+
-- 
2.30.2