From d56cf499ec0ffc07a0bd0428c9271c2c26d83905 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 10 Jul 2021 12:11:19 +0100 Subject: [PATCH] add ffadds decoding: - SVP64 trans manual creation of opcode with XO=0b01101 - add to power enums ISA list - add to minor 59 and SVP64 CSV --- openpower/isatables/RM-1P-2S1D.csv | 1 + openpower/isatables/minor_59.csv | 1 + src/openpower/decoder/power_enums.py | 1 + src/openpower/sv/trans/svp64.py | 13 ++++++++++++- 4 files changed, 15 insertions(+), 1 deletion(-) diff --git a/openpower/isatables/RM-1P-2S1D.csv b/openpower/isatables/RM-1P-2S1D.csv index 93ebb9ea..19b6f61e 100644 --- a/openpower/isatables/RM-1P-2S1D.csv +++ b/openpower/isatables/RM-1P-2S1D.csv @@ -79,6 +79,7 @@ divduo,,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 divwuo,,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 divdo,,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 divwo,,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 +ffadds,,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fdivs,,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fsubs,,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fadds,,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 diff --git a/openpower/isatables/minor_59.csv b/openpower/isatables/minor_59.csv index 0891f0a3..1605a58d 100644 --- a/openpower/isatables/minor_59.csv +++ b/openpower/isatables/minor_59.csv @@ -16,3 +16,4 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou -----00101,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,ffmadds,A, -----00110,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,ffnmsubs,A, -----00111,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,ffnmadds,A, +-----01101,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,ffadds,A, diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py index 41d712e2..48e437ba 100644 --- a/src/openpower/decoder/power_enums.py +++ b/src/openpower/decoder/power_enums.py @@ -242,6 +242,7 @@ _insns = [ "fadd", "fadds", "fsub", "fsubs", # FP add / sub "fcfids", "fcfidus", "fsqrts", "fres", "frsqrtes", # FP stuff "fmsubs", "fmadds", "fnmsubs", "fnmadds", # FP 3-arg + "ffadds", "ffsubs", "ffmuls", "ffdivs", # FFT FP 2-arg "ffmsubs", "ffmadds", "ffnmsubs", "ffnmadds", # FFT FP 3-arg "fmul", "fmuls", "fdiv", "fdivs", # FP mul / div "fmr", "fabs", "fnabs", "fneg", "fcpsgn", # FP move/abs/neg diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index 1c12ea7f..f3b13879 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -813,7 +813,17 @@ class SVP64Asm: opcode |= int(v30b_newfields[1]) << (32-16) # FRA opcode |= int(v30b_newfields[2]) << (32-21) # FRB opcode |= int(v30b_newfields[3]) << (32-26) # FRC - opcode |= 5 << (32-31) # bits 26-30 + opcode |= 0b00101 << (32-31) # bits 26-30 + if rc: + opcode |= 1 # Rc, bit 31. + yield ".long 0x%x" % opcode + # argh, sv.ffadds etc. need to be done manually + if v30b_op == 'ffadds': + opcode = 59 << (32-6) # bits 0..6 (MSB0) + opcode |= int(v30b_newfields[0]) << (32-11) # FRT + opcode |= int(v30b_newfields[1]) << (32-16) # FRA + opcode |= int(v30b_newfields[2]) << (32-21) # FRB + opcode |= 0b01101 << (32-31) # bits 26-30 if rc: opcode |= 1 # Rc, bit 31. yield ".long 0x%x" % opcode @@ -973,6 +983,7 @@ if __name__ == '__main__': lst = [ 'sv.fmadds 0.v, 8.v, 16.v, 4.v', 'svremap 8, 1, 1, 1', + 'sv.fadds 0.v, 8.v, 4.v', ] isa = SVP64Asm(lst, macros=macros) print ("list", list(isa)) -- 2.30.2