From d56cfeab09f56122940e06955a6fd6568463c27e Mon Sep 17 00:00:00 2001 From: R Veera Kumar Date: Tue, 14 Jun 2022 13:06:10 +0530 Subject: [PATCH] Add SVG vector image version of zolc_svp64_extrav.jpg --- openpower/sv/zolc_svp64_extrav.svg | 1462 ++++++++++++++++++++++++++++ 1 file changed, 1462 insertions(+) create mode 100644 openpower/sv/zolc_svp64_extrav.svg diff --git a/openpower/sv/zolc_svp64_extrav.svg b/openpower/sv/zolc_svp64_extrav.svg new file mode 100644 index 000000000..9932abadc --- /dev/null +++ b/openpower/sv/zolc_svp64_extrav.svg @@ -0,0 +1,1462 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + DRAFT + * LOAD/STORE Inc(Snitch Style) + * TEST-ZERO(EXTRA-V Style) + * LOOPS(ZOLC Style) + * PE runs ZOLCand Snitch Style + * PE SEnds viaOpen CAPI to CPU,receives as well? + * OPENCAPI direct to CPU: Queues(Snitch Style) + * L1/L2 Not involved! + * Regfile Not involved! + * CPU could send direct to Memory?(depends on algorithm) + * CPU not idle:coordinatingParallel Processing,Managing RADIX MMUof PEs + + + MEM + L1/L2 + REGFILE + Main CPU + + MEM + PE Reg + PE + LOAD/INC + SEND + STORE/INC + TEST ZERO? + Open CAPI + Open CAPI + CPU + MUL + SEND + Main CPU + PE + LOAD/INC + TEST ZERO? + MUL + STORE/INC + MEM + PE Reg + CPU + (CoordinatingOpen CAPI) + + LOOP + LOAD/INC + TEST ZERO? + MUL + STORE/INC + + + + + + + + + + + + + + + + + + + + + CPU + LOAD/INC + TEST ZERO? + MUL + STORE/INC + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + L1/L2 + + + + + REGFILE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + -- 2.30.2