From d56e77c180aeca0ff1ba271378424787345ec0b8 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sun, 10 Feb 2008 14:15:42 -0800 Subject: [PATCH] Rename cache files for brevity and consistency with rest of tree. --HG-- rename : src/mem/cache/base_cache.cc => src/mem/cache/base.cc rename : src/mem/cache/base_cache.hh => src/mem/cache/base.hh rename : src/mem/cache/cache_blk.cc => src/mem/cache/blk.cc rename : src/mem/cache/cache_blk.hh => src/mem/cache/blk.hh rename : src/mem/cache/cache_builder.cc => src/mem/cache/builder.cc rename : src/mem/cache/miss/mshr.cc => src/mem/cache/mshr.cc rename : src/mem/cache/miss/mshr.hh => src/mem/cache/mshr.hh rename : src/mem/cache/miss/mshr_queue.cc => src/mem/cache/mshr_queue.cc rename : src/mem/cache/miss/mshr_queue.hh => src/mem/cache/mshr_queue.hh rename : src/mem/cache/prefetch/base_prefetcher.cc => src/mem/cache/prefetch/base.cc rename : src/mem/cache/prefetch/base_prefetcher.hh => src/mem/cache/prefetch/base.hh rename : src/mem/cache/prefetch/ghb_prefetcher.cc => src/mem/cache/prefetch/ghb.cc rename : src/mem/cache/prefetch/ghb_prefetcher.hh => src/mem/cache/prefetch/ghb.hh rename : src/mem/cache/prefetch/stride_prefetcher.cc => src/mem/cache/prefetch/stride.cc rename : src/mem/cache/prefetch/stride_prefetcher.hh => src/mem/cache/prefetch/stride.hh rename : src/mem/cache/prefetch/tagged_prefetcher.cc => src/mem/cache/prefetch/tagged.cc rename : src/mem/cache/prefetch/tagged_prefetcher.hh => src/mem/cache/prefetch/tagged.hh rename : src/mem/cache/tags/base_tags.cc => src/mem/cache/tags/base.cc rename : src/mem/cache/tags/base_tags.hh => src/mem/cache/tags/base.hh rename : src/mem/cache/tags/Repl.py => src/mem/cache/tags/iic_repl/Repl.py rename : src/mem/cache/tags/repl/gen.cc => src/mem/cache/tags/iic_repl/gen.cc rename : src/mem/cache/tags/repl/gen.hh => src/mem/cache/tags/iic_repl/gen.hh rename : src/mem/cache/tags/repl/repl.hh => src/mem/cache/tags/iic_repl/repl.hh extra : convert_revision : ff7a35cc155a8d80317563c45cebe405984eac62 --- src/mem/cache/SConscript | 8 +++++--- src/mem/cache/{base_cache.cc => base.cc} | 0 src/mem/cache/{base_cache.hh => base.hh} | 0 src/mem/cache/{cache_blk.cc => blk.cc} | 0 src/mem/cache/{cache_blk.hh => blk.hh} | 0 src/mem/cache/{cache_builder.cc => builder.cc} | 0 src/mem/cache/{miss => }/mshr.cc | 0 src/mem/cache/{miss => }/mshr.hh | 0 src/mem/cache/{miss => }/mshr_queue.cc | 0 src/mem/cache/{miss => }/mshr_queue.hh | 0 src/mem/cache/prefetch/SConscript | 8 ++++---- .../prefetch/{base_prefetcher.cc => base.cc} | 0 .../prefetch/{base_prefetcher.hh => base.hh} | 0 .../prefetch/{ghb_prefetcher.cc => ghb.cc} | 0 .../prefetch/{ghb_prefetcher.hh => ghb.hh} | 0 .../{stride_prefetcher.cc => stride.cc} | 0 .../{stride_prefetcher.hh => stride.hh} | 0 .../{tagged_prefetcher.cc => tagged.cc} | 0 .../{tagged_prefetcher.hh => tagged.hh} | 0 src/mem/cache/tags/Repl.py | 11 ----------- src/mem/cache/tags/SConscript | 6 +++--- src/mem/cache/tags/{base_tags.cc => base.cc} | 0 src/mem/cache/tags/{base_tags.hh => base.hh} | 0 .../{miss/SConscript => tags/iic_repl/Repl.py} | 17 +++++++++++------ src/mem/cache/tags/{repl => iic_repl}/gen.cc | 0 src/mem/cache/tags/{repl => iic_repl}/gen.hh | 0 src/mem/cache/tags/{repl => iic_repl}/repl.hh | 0 27 files changed, 23 insertions(+), 27 deletions(-) rename src/mem/cache/{base_cache.cc => base.cc} (100%) rename src/mem/cache/{base_cache.hh => base.hh} (100%) rename src/mem/cache/{cache_blk.cc => blk.cc} (100%) rename src/mem/cache/{cache_blk.hh => blk.hh} (100%) rename src/mem/cache/{cache_builder.cc => builder.cc} (100%) rename src/mem/cache/{miss => }/mshr.cc (100%) rename src/mem/cache/{miss => }/mshr.hh (100%) rename src/mem/cache/{miss => }/mshr_queue.cc (100%) rename src/mem/cache/{miss => }/mshr_queue.hh (100%) rename src/mem/cache/prefetch/{base_prefetcher.cc => base.cc} (100%) rename src/mem/cache/prefetch/{base_prefetcher.hh => base.hh} (100%) rename src/mem/cache/prefetch/{ghb_prefetcher.cc => ghb.cc} (100%) rename src/mem/cache/prefetch/{ghb_prefetcher.hh => ghb.hh} (100%) rename src/mem/cache/prefetch/{stride_prefetcher.cc => stride.cc} (100%) rename src/mem/cache/prefetch/{stride_prefetcher.hh => stride.hh} (100%) rename src/mem/cache/prefetch/{tagged_prefetcher.cc => tagged.cc} (100%) rename src/mem/cache/prefetch/{tagged_prefetcher.hh => tagged.hh} (100%) delete mode 100644 src/mem/cache/tags/Repl.py rename src/mem/cache/tags/{base_tags.cc => base.cc} (100%) rename src/mem/cache/tags/{base_tags.hh => base.hh} (100%) rename src/mem/cache/{miss/SConscript => tags/iic_repl/Repl.py} (79%) rename src/mem/cache/tags/{repl => iic_repl}/gen.cc (100%) rename src/mem/cache/tags/{repl => iic_repl}/gen.hh (100%) rename src/mem/cache/tags/{repl => iic_repl}/repl.hh (100%) diff --git a/src/mem/cache/SConscript b/src/mem/cache/SConscript index d5899b623..3b8bdb0c8 100644 --- a/src/mem/cache/SConscript +++ b/src/mem/cache/SConscript @@ -32,10 +32,12 @@ Import('*') SimObject('BaseCache.py') -Source('base_cache.cc') +Source('base.cc') Source('cache.cc') -Source('cache_blk.cc') -Source('cache_builder.cc') +Source('blk.cc') +Source('builder.cc') +Source('mshr.cc') +Source('mshr_queue.cc') TraceFlag('Cache') TraceFlag('CachePort') diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base.cc similarity index 100% rename from src/mem/cache/base_cache.cc rename to src/mem/cache/base.cc diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base.hh similarity index 100% rename from src/mem/cache/base_cache.hh rename to src/mem/cache/base.hh diff --git a/src/mem/cache/cache_blk.cc b/src/mem/cache/blk.cc similarity index 100% rename from src/mem/cache/cache_blk.cc rename to src/mem/cache/blk.cc diff --git a/src/mem/cache/cache_blk.hh b/src/mem/cache/blk.hh similarity index 100% rename from src/mem/cache/cache_blk.hh rename to src/mem/cache/blk.hh diff --git a/src/mem/cache/cache_builder.cc b/src/mem/cache/builder.cc similarity index 100% rename from src/mem/cache/cache_builder.cc rename to src/mem/cache/builder.cc diff --git a/src/mem/cache/miss/mshr.cc b/src/mem/cache/mshr.cc similarity index 100% rename from src/mem/cache/miss/mshr.cc rename to src/mem/cache/mshr.cc diff --git a/src/mem/cache/miss/mshr.hh b/src/mem/cache/mshr.hh similarity index 100% rename from src/mem/cache/miss/mshr.hh rename to src/mem/cache/mshr.hh diff --git a/src/mem/cache/miss/mshr_queue.cc b/src/mem/cache/mshr_queue.cc similarity index 100% rename from src/mem/cache/miss/mshr_queue.cc rename to src/mem/cache/mshr_queue.cc diff --git a/src/mem/cache/miss/mshr_queue.hh b/src/mem/cache/mshr_queue.hh similarity index 100% rename from src/mem/cache/miss/mshr_queue.hh rename to src/mem/cache/mshr_queue.hh diff --git a/src/mem/cache/prefetch/SConscript b/src/mem/cache/prefetch/SConscript index 8a7f1232c..7314b5ccf 100644 --- a/src/mem/cache/prefetch/SConscript +++ b/src/mem/cache/prefetch/SConscript @@ -30,8 +30,8 @@ Import('*') -Source('base_prefetcher.cc') -Source('ghb_prefetcher.cc') -Source('stride_prefetcher.cc') -Source('tagged_prefetcher.cc') +Source('base.cc') +Source('ghb.cc') +Source('stride.cc') +Source('tagged.cc') diff --git a/src/mem/cache/prefetch/base_prefetcher.cc b/src/mem/cache/prefetch/base.cc similarity index 100% rename from src/mem/cache/prefetch/base_prefetcher.cc rename to src/mem/cache/prefetch/base.cc diff --git a/src/mem/cache/prefetch/base_prefetcher.hh b/src/mem/cache/prefetch/base.hh similarity index 100% rename from src/mem/cache/prefetch/base_prefetcher.hh rename to src/mem/cache/prefetch/base.hh diff --git a/src/mem/cache/prefetch/ghb_prefetcher.cc b/src/mem/cache/prefetch/ghb.cc similarity index 100% rename from src/mem/cache/prefetch/ghb_prefetcher.cc rename to src/mem/cache/prefetch/ghb.cc diff --git a/src/mem/cache/prefetch/ghb_prefetcher.hh b/src/mem/cache/prefetch/ghb.hh similarity index 100% rename from src/mem/cache/prefetch/ghb_prefetcher.hh rename to src/mem/cache/prefetch/ghb.hh diff --git a/src/mem/cache/prefetch/stride_prefetcher.cc b/src/mem/cache/prefetch/stride.cc similarity index 100% rename from src/mem/cache/prefetch/stride_prefetcher.cc rename to src/mem/cache/prefetch/stride.cc diff --git a/src/mem/cache/prefetch/stride_prefetcher.hh b/src/mem/cache/prefetch/stride.hh similarity index 100% rename from src/mem/cache/prefetch/stride_prefetcher.hh rename to src/mem/cache/prefetch/stride.hh diff --git a/src/mem/cache/prefetch/tagged_prefetcher.cc b/src/mem/cache/prefetch/tagged.cc similarity index 100% rename from src/mem/cache/prefetch/tagged_prefetcher.cc rename to src/mem/cache/prefetch/tagged.cc diff --git a/src/mem/cache/prefetch/tagged_prefetcher.hh b/src/mem/cache/prefetch/tagged.hh similarity index 100% rename from src/mem/cache/prefetch/tagged_prefetcher.hh rename to src/mem/cache/prefetch/tagged.hh diff --git a/src/mem/cache/tags/Repl.py b/src/mem/cache/tags/Repl.py deleted file mode 100644 index b76aa1d6e..000000000 --- a/src/mem/cache/tags/Repl.py +++ /dev/null @@ -1,11 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -class Repl(SimObject): - type = 'Repl' - abstract = True - -class GenRepl(Repl): - type = 'GenRepl' - fresh_res = Param.Int("Fresh pool residency time") - num_pools = Param.Int("Number of priority pools") - pool_res = Param.Int("Pool residency time") diff --git a/src/mem/cache/tags/SConscript b/src/mem/cache/tags/SConscript index 18ed8408b..9153d97e7 100644 --- a/src/mem/cache/tags/SConscript +++ b/src/mem/cache/tags/SConscript @@ -30,7 +30,7 @@ Import('*') -Source('base_tags.cc') +Source('base.cc') Source('fa_lru.cc') Source('iic.cc') Source('lru.cc') @@ -38,8 +38,8 @@ Source('split.cc') Source('split_lifo.cc') Source('split_lru.cc') -SimObject('Repl.py') -Source('repl/gen.cc') +SimObject('iic_repl/Repl.py') +Source('iic_repl/gen.cc') TraceFlag('IIC') TraceFlag('IICMore') diff --git a/src/mem/cache/tags/base_tags.cc b/src/mem/cache/tags/base.cc similarity index 100% rename from src/mem/cache/tags/base_tags.cc rename to src/mem/cache/tags/base.cc diff --git a/src/mem/cache/tags/base_tags.hh b/src/mem/cache/tags/base.hh similarity index 100% rename from src/mem/cache/tags/base_tags.hh rename to src/mem/cache/tags/base.hh diff --git a/src/mem/cache/miss/SConscript b/src/mem/cache/tags/iic_repl/Repl.py similarity index 79% rename from src/mem/cache/miss/SConscript rename to src/mem/cache/tags/iic_repl/Repl.py index 376d670cd..4c333e897 100644 --- a/src/mem/cache/miss/SConscript +++ b/src/mem/cache/tags/iic_repl/Repl.py @@ -1,6 +1,4 @@ -# -*- mode:python -*- - -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2005-2008 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -28,7 +26,14 @@ # # Authors: Nathan Binkert -Import('*') +from m5.SimObject import SimObject +from m5.params import * +class Repl(SimObject): + type = 'Repl' + abstract = True -Source('mshr.cc') -Source('mshr_queue.cc') +class GenRepl(Repl): + type = 'GenRepl' + fresh_res = Param.Int("Fresh pool residency time") + num_pools = Param.Int("Number of priority pools") + pool_res = Param.Int("Pool residency time") diff --git a/src/mem/cache/tags/repl/gen.cc b/src/mem/cache/tags/iic_repl/gen.cc similarity index 100% rename from src/mem/cache/tags/repl/gen.cc rename to src/mem/cache/tags/iic_repl/gen.cc diff --git a/src/mem/cache/tags/repl/gen.hh b/src/mem/cache/tags/iic_repl/gen.hh similarity index 100% rename from src/mem/cache/tags/repl/gen.hh rename to src/mem/cache/tags/iic_repl/gen.hh diff --git a/src/mem/cache/tags/repl/repl.hh b/src/mem/cache/tags/iic_repl/repl.hh similarity index 100% rename from src/mem/cache/tags/repl/repl.hh rename to src/mem/cache/tags/iic_repl/repl.hh -- 2.30.2