From d58ba677c6309e5bc6e2353f91bed2d06f573311 Mon Sep 17 00:00:00 2001 From: whitequark Date: Mon, 3 Jun 2019 03:01:56 +0000 Subject: [PATCH] vendor.fpga.lattice_ice40: enable SystemVerilog when reading .sv files. --- nmigen/vendor/fpga/lattice_ice40.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nmigen/vendor/fpga/lattice_ice40.py b/nmigen/vendor/fpga/lattice_ice40.py index 9a8469c..c80076d 100644 --- a/nmigen/vendor/fpga/lattice_ice40.py +++ b/nmigen/vendor/fpga/lattice_ice40.py @@ -51,7 +51,7 @@ class LatticeICE40Platform(TemplatedPlatform): {% if file.endswith(".v") -%} read_verilog {{get_override("read_opts")|join(" ")}} {{file}} {% elif file.endswith(".sv") -%} - read_verilog {{get_override("read_opts")|join(" ")}} {{file}} + read_verilog -sv {{get_override("read_opts")|join(" ")}} {{file}} {% endif %} {% endfor %} read_ilang {{name}}.il -- 2.30.2