From d5a21a7522daf4978c344490983157efd65b3a2e Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Sun, 23 Feb 2020 06:54:48 -0800 Subject: [PATCH] Converting litex to use Python modules. --- litex/data/__init__.py | 2 ++ litex/data/find.py | 13 +++++++++++++ litex/soc/cores/cpu/blackparrot/core.py | 3 ++- litex/soc/cores/cpu/lm32/core.py | 8 ++++---- litex/soc/cores/cpu/microwatt/core.py | 3 ++- litex/soc/cores/cpu/mor1kx/core.py | 1 + litex/soc/cores/cpu/picorv32/core.py | 4 ++-- litex/soc/cores/cpu/rocket/core.py | 4 ++-- litex/soc/cores/cpu/vexriscv/core.py | 3 ++- litex_setup.py | 12 +++++++++++- 10 files changed, 41 insertions(+), 12 deletions(-) create mode 100644 litex/data/__init__.py create mode 100644 litex/data/find.py diff --git a/litex/data/__init__.py b/litex/data/__init__.py new file mode 100644 index 00000000..c9b5ae90 --- /dev/null +++ b/litex/data/__init__.py @@ -0,0 +1,2 @@ +# https://packaging.python.org/guides/packaging-namespace-packages/#pkgutil-style-namespace-packages +__path__ = __import__('pkgutil').extend_path(__path__, __name__) diff --git a/litex/data/find.py b/litex/data/find.py new file mode 100644 index 00000000..da7ed981 --- /dev/null +++ b/litex/data/find.py @@ -0,0 +1,13 @@ +def find_data(data_type, data_name): + imp = "from litex.data.{} import {} as dm".format(data_type, data_name) + try: + exec(imp) + return dm.data_location + except ImportError as e: + raise ImportError("""\ +litex-data-{dt}-{dn} module not install! Unable to use {dn} {dt}. +{e} + +You can install this by running; + pip install git+https://github.com/litex-hub/litex-data-{dt}-{dn}.git +""".format(dt=data_type, dn=data_name, e=e)) diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py index 89766489..e55e6252 100644 --- a/litex/soc/cores/cpu/blackparrot/core.py +++ b/litex/soc/cores/cpu/blackparrot/core.py @@ -32,6 +32,7 @@ import os from migen import * +from litex.data.find import find_data from litex.soc.interconnect import axi from litex.soc.interconnect import wishbone from litex.soc.cores.cpu import CPU @@ -115,7 +116,7 @@ class BlackParrotRV64(CPU): @staticmethod def add_sources(platform, variant="standard"): - filename = os.path.join(os.path.abspath(os.path.dirname(__file__)), "flist_litex.verilator") + filename = os.path.join(find_data("cpu", "blackparrot"), "flist_litex.verilator") with open(filename) as openfileobject: for line in openfileobject: temp = line diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py index 9ef8333b..75e7ba8c 100644 --- a/litex/soc/cores/cpu/lm32/core.py +++ b/litex/soc/cores/cpu/lm32/core.py @@ -9,6 +9,7 @@ import os from migen import * +from litex.data.find import find_data from litex.soc.interconnect import wishbone from litex.soc.cores.cpu import CPU @@ -96,9 +97,8 @@ class LM32(CPU): @staticmethod def add_sources(platform, variant): - vdir = os.path.join( - os.path.abspath(os.path.dirname(__file__)), "verilog") - platform.add_sources(os.path.join(vdir, "submodule", "rtl"), + vdir = find_data("cpu", "lm32") + platform.add_sources(os.path.join(vdir, "rtl"), "lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v", @@ -117,7 +117,7 @@ class LM32(CPU): "lm32_debug.v", "lm32_itlb.v", "lm32_dtlb.v") - platform.add_verilog_include_path(os.path.join(vdir, "submodule", "rtl")) + platform.add_verilog_include_path(os.path.join(vdir, "rtl")) if variant == "minimal": platform.add_verilog_include_path(os.path.join(vdir, "config_minimal")) elif variant == "lite": diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py index 584ad445..aa00ee17 100644 --- a/litex/soc/cores/cpu/microwatt/core.py +++ b/litex/soc/cores/cpu/microwatt/core.py @@ -6,6 +6,7 @@ import os from migen import * +from litex.data.find import find_data from litex.soc.interconnect import wishbone from litex.soc.cores.cpu import CPU @@ -98,7 +99,7 @@ class Microwatt(CPU): @staticmethod def add_sources(platform): - sdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "sources") + sdir = os.path.join(find_data("cpu", "microwatt"), "sources") platform.add_sources(sdir, # Common / Types / Helpers "decode_types.vhdl", diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py index c82b6e55..4fe41b36 100644 --- a/litex/soc/cores/cpu/mor1kx/core.py +++ b/litex/soc/cores/cpu/mor1kx/core.py @@ -8,6 +8,7 @@ import os from migen import * +from litex.data.find import find_data from litex.soc.interconnect import wishbone from litex.soc.cores.cpu import CPU diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py index 304f6c14..47017ac6 100644 --- a/litex/soc/cores/cpu/picorv32/core.py +++ b/litex/soc/cores/cpu/picorv32/core.py @@ -11,6 +11,7 @@ import os from migen import * +from litex.data.find import find_data from litex.soc.interconnect import wishbone from litex.soc.cores.cpu import CPU @@ -179,8 +180,7 @@ class PicoRV32(CPU): @staticmethod def add_sources(platform): - vdir = os.path.join( - os.path.abspath(os.path.dirname(__file__)), "verilog") + vdir = find_data("cpu", "picorv32") platform.add_source(os.path.join(vdir, "picorv32.v")) def do_finalize(self): diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py index 14bab0f4..dff3fe70 100644 --- a/litex/soc/cores/cpu/rocket/core.py +++ b/litex/soc/cores/cpu/rocket/core.py @@ -33,6 +33,7 @@ import os from migen import * +from litex.data.find import find_data from litex.soc.interconnect import axi from litex.soc.interconnect import wishbone from litex.soc.cores.cpu import CPU @@ -238,8 +239,7 @@ class RocketRV64(CPU): @staticmethod def add_sources(platform, variant="standard"): - vdir = os.path.join( - os.path.abspath(os.path.dirname(__file__)), "verilog") + vdir = find_data("cpu", "rocket") platform.add_sources( os.path.join(vdir, "generated-src"), CPU_VARIANTS[variant] + ".v", diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py index 4e0bbc0a..42328d19 100644 --- a/litex/soc/cores/cpu/vexriscv/core.py +++ b/litex/soc/cores/cpu/vexriscv/core.py @@ -12,6 +12,7 @@ import os from migen import * +from litex.data.find import find_data from litex.soc.interconnect import wishbone from litex.soc.interconnect.csr import * from litex.soc.cores.cpu import CPU @@ -246,7 +247,7 @@ class VexRiscv(CPU, AutoCSR): @staticmethod def add_sources(platform, variant="standard"): cpu_filename = CPU_VARIANTS[variant] + ".v" - vdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "verilog") + vdir = find_data("cpu", "vexriscv") platform.add_source(os.path.join(vdir, cpu_filename)) def use_external_variant(self, variant_filename): diff --git a/litex_setup.py b/litex_setup.py index 60582955..ca1d4f49 100755 --- a/litex_setup.py +++ b/litex_setup.py @@ -18,7 +18,8 @@ repos = [ ("migen", ("https://github.com/m-labs/", True, True)), # LiteX SoC builder - ("litex", ("https://github.com/enjoy-digital/", True, True)), + ('litex-data-software-compiler_rt', ("https://github.com/litex-hub/", False, True)) + ("litex", ("https://github.com/enjoy-digital/", False, True)), # LiteX cores ecosystem ("liteeth", ("https://github.com/enjoy-digital/", False, True)), @@ -34,6 +35,15 @@ repos = [ # LiteX boards support ("litex-boards", ("https://github.com/litex-hub/", False, True)), + + # Optional LiteX data + ('litex-data-cpu-blackparrot', ("https://github.com/litex-hub/", False, True)) + ('litex-data-cpu-mor1kx', ("https://github.com/litex-hub/", False, True)) + ('litex-data-cpu-lm32', ("https://github.com/litex-hub/", False, True)) + ('litex-data-cpu-microwatt', ("https://github.com/litex-hub/", False, True)) + ('litex-data-cpu-picorv32', ("https://github.com/litex-hub/", False, True)) + ('litex-data-cpu-rocket', ("https://github.com/litex-hub/", False, True)) + ('litex-data-misc-tapcfg', ("https://github.com/litex-hub/", False, True)) ] repos = OrderedDict(repos) -- 2.30.2