From d5b02d90621be7f7f4fd8ca938632c0bbe38d3d7 Mon Sep 17 00:00:00 2001 From: Venkataramanan Kumar Date: Sun, 5 Aug 2012 12:29:52 +0000 Subject: [PATCH] Document AMD btver2 From-SVN: r190151 --- gcc/ChangeLog | 5 +++++ gcc/doc/extend.texi | 6 ++++++ gcc/doc/invoke.texi | 5 +++++ 3 files changed, 16 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9292c7b651a..e228bfb2c6d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2012-08-05 Venkataramanan Kumar + + * doc/invoke.texi: Document AMD btver2. + * doc/extend.texi: Document AMD btver1 and btver2. + 2012-08-04 Sandra Loosemore Richard Sandiford diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 5d851a7386b..615321fcf83 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -9560,6 +9560,9 @@ AMD family 10h Shanghai CPU. @item istanbul AMD family 10h Istanbul CPU. +@item btver1 +AMD family 14h CPU. + @item amdfam15h AMD family 15h CPU. @@ -9568,6 +9571,9 @@ AMD family 15h Bulldozer version 1. @item bdver2 AMD family 15h Bulldozer version 2. + +@item btver2 +AMD family 16h CPU. @end table Here is an example: diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 857fc4029a8..379761c59ed 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -13304,6 +13304,11 @@ CPUs based on AMD Family 14h cores with x86-64 instruction set support. (This supersets MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM and 64-bit instruction set extensions.) +@item btver2 +CPUs based on AMD Family 16h cores with x86-64 instruction set support. This +includes MOVBE, F16C, BMI, AVX, PCL_MUL, AES, SSE4.2, SSE4.1, CX16, ABM, +SSE4A, SSSE3, SSE3, SSE2, SSE, MMX and 64-bit instruction set extensions. + @item winchip-c6 IDT WinChip C6 CPU, dealt in same way as i486 with additional MMX instruction set support. -- 2.30.2