From d5ba553707e04e9f7268534da02242f95ca91897 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 14 May 2020 11:04:04 +0100 Subject: [PATCH] add TODO comments on Logical pipeline --- src/soc/alu/main_stage.py | 3 +-- src/soc/logical/main_stage.py | 12 +++++++++--- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/src/soc/alu/main_stage.py b/src/soc/alu/main_stage.py index 71fa1f9d..456e652f 100644 --- a/src/soc/alu/main_stage.py +++ b/src/soc/alu/main_stage.py @@ -1,6 +1,6 @@ # This stage is intended to do most of the work of executing the Arithmetic # instructions. This would be like the additions, compares, and sign-extension -# and shifting, as well as carry and overflow generation. This module +# as well as carry and overflow generation. This module # however should not gate the carry or overflow, that's up to the # output stage from nmigen import (Module, Signal, Cat, Repl, Mux, Const) @@ -10,7 +10,6 @@ from ieee754.part.partsig import PartitionedSignal from soc.decoder.power_enums import InternalOp - class ALUMainStage(PipeModBase): def __init__(self, pspec): super().__init__(pspec, "main") diff --git a/src/soc/logical/main_stage.py b/src/soc/logical/main_stage.py index 622216bb..7b43cf31 100644 --- a/src/soc/logical/main_stage.py +++ b/src/soc/logical/main_stage.py @@ -1,7 +1,7 @@ # This stage is intended to do most of the work of executing Logical -# instructions. This is OR, AND and XOR, however input and output -# stages also perform bit-negation on input(s) and output, as well as -# carry and overflow generation. +# instructions. This is OR, AND, XOR, POPCNT, PRTY, CMPB, BPERMD, CNTLZ +# however input and output stages also perform bit-negation on input(s) +# and output, as well as carry and overflow generation. # This module however should not gate the carry or overflow, that's up # to the output stage @@ -41,6 +41,12 @@ class LogicalMainStage(PipeModBase): # TODO with m.Case(InternalOp.OP_POPCNT): ###### parity ####### # TODO with m.Case(InternalOp.OP_PRTY): + ###### cmpb ####### + # TODO with m.Case(InternalOp.OP_CMPB): + ###### cntlz ####### + # TODO with m.Case(InternalOp.OP_CNTZ): + ###### bpermd ####### + # TODO with m.Case(InternalOp.OP_BPERM): - not in microwatt ###### sticky overflow and context, both pass-through ##### -- 2.30.2