From d5caa0f89f44d3dbf4944258d4ce0c7f6559ce6c Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Wed, 13 Jul 2016 00:06:51 +0200 Subject: [PATCH] re PR tree-optimization/68961 (Test case gcc.target/powerpc/pr60203.c fails since r231674) PR rtl-optimization/68961 * config/i386/sse.md (movsd/movhpd to movupd peephole2s): Add new peephole variant. Use sse_reg_operand predicates. From-SVN: r238268 --- gcc/ChangeLog | 8 +++++++- gcc/config/i386/sse.md | 20 ++++++++++++++++---- 2 files changed, 23 insertions(+), 5 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6cb8da203fa..0b7518f24b1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2016-07-13 Uros Bizjak + + PR rtl-optimization/68961 + * config/i386/sse.md (movsd/movhpd to movupd peephole2s): Add new + peephole variant. Use sse_reg_operand predicates. + 2016-07-12 Uros Bizjak * config/i386/predicates.md (x86_64_immediate_operand) @@ -41,7 +47,7 @@ loops. 2016-07-12 Steven Bosscher - Richard Biener + Richard Biener PR tree-optimization/23286 PR tree-optimization/70159 diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index c1ea04ffca8..6b898dc0513 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1169,10 +1169,10 @@ ;; Merge movsd/movhpd to movupd for TARGET_SSE_UNALIGNED_LOAD_OPTIMAL targets. (define_peephole2 - [(set (match_operand:V2DF 0 "register_operand") + [(set (match_operand:V2DF 0 "sse_reg_operand") (vec_concat:V2DF (match_operand:DF 1 "memory_operand") (match_operand:DF 4 "const0_operand"))) - (set (match_operand:V2DF 2 "register_operand") + (set (match_operand:V2DF 2 "sse_reg_operand") (vec_concat:V2DF (vec_select:DF (match_dup 2) (parallel [(const_int 0)])) (match_operand:DF 3 "memory_operand")))] @@ -1181,13 +1181,25 @@ [(set (match_dup 2) (match_dup 4))] "operands[4] = adjust_address (operands[1], V2DFmode, 0);") +(define_peephole2 + [(set (match_operand:DF 0 "sse_reg_operand") + (match_operand:DF 1 "memory_operand")) + (set (match_operand:V2DF 2 "sse_reg_operand") + (vec_concat:V2DF (match_operand:DF 4 "sse_reg_operand") + (match_operand:DF 3 "memory_operand")))] + "TARGET_SSE2 && TARGET_SSE_UNALIGNED_LOAD_OPTIMAL + && REGNO (operands[4]) == REGNO (operands[2]) + && ix86_operands_ok_for_move_multiple (operands, true, DFmode)" + [(set (match_dup 2) (match_dup 4))] + "operands[4] = adjust_address (operands[1], V2DFmode, 0);") + ;; Merge movlpd/movhpd to movupd for TARGET_SSE_UNALIGNED_STORE_OPTIMAL targets. (define_peephole2 [(set (match_operand:DF 0 "memory_operand") - (vec_select:DF (match_operand:V2DF 1 "register_operand") + (vec_select:DF (match_operand:V2DF 1 "sse_reg_operand") (parallel [(const_int 0)]))) (set (match_operand:DF 2 "memory_operand") - (vec_select:DF (match_operand:V2DF 3 "register_operand") + (vec_select:DF (match_operand:V2DF 3 "sse_reg_operand") (parallel [(const_int 1)])))] "TARGET_SSE2 && TARGET_SSE_UNALIGNED_STORE_OPTIMAL && ix86_operands_ok_for_move_multiple (operands, false, DFmode)" -- 2.30.2