From d5d62c713b127cd17a99ba124bd7320ab98f46c8 Mon Sep 17 00:00:00 2001 From: klehman Date: Sat, 25 Sep 2021 10:32:33 -0400 Subject: [PATCH] moved pc_i and sv_state to constructor, remove hdl_state_run --- src/soc/simple/test/test_runner.py | 110 ++++------------------------- 1 file changed, 15 insertions(+), 95 deletions(-) diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py index cb9abbd6..ff823c66 100644 --- a/src/soc/simple/test/test_runner.py +++ b/src/soc/simple/test/test_runner.py @@ -124,93 +124,6 @@ def get_dmi(dmi, addr): return data -def run_hdl_state(dut, test, issuer, pc_i, svstate_i, instructions): - """run_hdl_state - runs a TestIssuer nmigen HDL simulation - """ - - imem = issuer.imem._get_memory() - core = issuer.core - dmi = issuer.dbg.dmi - pdecode2 = issuer.pdecode2 - l0 = core.l0 - hdl_states = [] - - # establish the TestIssuer context (mem, regs etc) - - pc = 0 # start address - counter = 0 # test to pause/start - - yield from setup_i_memory(imem, pc, instructions) - yield from setup_tst_memory(l0, test.mem) - yield from setup_regs(pdecode2, core, test) - - # set PC and SVSTATE - yield pc_i.eq(pc) - yield issuer.pc_i.ok.eq(1) - - # copy initial SVSTATE - initial_svstate = copy(test.svstate) - if isinstance(initial_svstate, int): - initial_svstate = SVP64State(initial_svstate) - yield svstate_i.eq(initial_svstate.value) - yield issuer.svstate_i.ok.eq(1) - yield - - print("instructions", instructions) - - # run the loop of the instructions on the current test - index = (yield issuer.cur_state.pc) // 4 - while index < len(instructions): - ins, code = instructions[index] - - print("hdl instr: 0x{:X}".format(ins & 0xffffffff)) - print(index, code) - - if counter == 0: - # start the core - yield - yield from set_dmi(dmi, DBGCore.CTRL, - 1<= len(instructions): - print ("index over, send dmi stop") - # stop at end - yield from set_dmi(dmi, DBGCore.CTRL, - 1<