From d5e8c0e6d33de71493855eca72fcc454a67a6140 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 7 Aug 2019 21:33:56 -0700
Subject: [PATCH] Remove ice40_unlut call, simply do equiv_opt on synth_ice40

---
 tests/opt/opt_lut.ys | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/tests/opt/opt_lut.ys b/tests/opt/opt_lut.ys
index 59b12c351..a9fccbb62 100644
--- a/tests/opt/opt_lut.ys
+++ b/tests/opt/opt_lut.ys
@@ -1,4 +1,2 @@
 read_verilog opt_lut.v
-synth_ice40
-ice40_unlut
-equiv_opt -map +/ice40/cells_sim.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3
+equiv_opt -map +/ice40/cells_sim.v -assert synth_ice40
-- 
2.30.2