From d5ffc11fcbd43cb72e3ba55a52bb8df6374a8745 Mon Sep 17 00:00:00 2001 From: Jiangshuai Li Date: Tue, 12 Jul 2022 09:54:58 +0800 Subject: [PATCH] gdb/csky complete csky_dwarf_reg_to_regnum For csky arch, the correspondence between Dwarf registers and GDB registers are as follows: dwarf regnos 0~31 ==> gdb regs r0~r31 dwarf regno CSKY_HI_REGNUM(36) ==> gdb reg hi dwarf regno CSKY_LO_REGNUM(37) ==> gdb reg hi dwarf regno CSKY_PC_REGNUM(72) ==> gdb reg pc dwarf regnos FV_PSEUDO_REGNO_FIRST(74)~FV_PSEUDO_REGNO_LAST(201) ==> gdb regs s0~s127 (pseudo regs for float and vector regs) other dwarf regnos have no corresponding gdb regs to them. --- gdb/csky-tdep.c | 25 ++++++++++++++++++++++--- gdb/csky-tdep.h | 4 ++++ 2 files changed, 26 insertions(+), 3 deletions(-) diff --git a/gdb/csky-tdep.c b/gdb/csky-tdep.c index b63ff7ccd44..502b01e33e1 100644 --- a/gdb/csky-tdep.c +++ b/gdb/csky-tdep.c @@ -2556,9 +2556,28 @@ csky_register_reggroup_p (struct gdbarch *gdbarch, int regnum, static int csky_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int dw_reg) { - if (dw_reg < 0 || dw_reg >= CSKY_NUM_REGS) - return -1; - return dw_reg; + /* For GPRs. */ + if (dw_reg >= CSKY_R0_REGNUM && dw_reg <= (CSKY_R0_REGNUM + 31)) + return dw_reg; + + /* For Hi, Lo, PC. */ + if ((dw_reg == CSKY_HI_REGNUM) || (dw_reg == CSKY_LO_REGNUM) + || (dw_reg == CSKY_PC_REGNUM)) + return dw_reg; + + /* For Float and Vector pseudo registers. */ + if ((dw_reg >= FV_PSEUDO_REGNO_FIRST) && (dw_reg <= FV_PSEUDO_REGNO_LAST)) + { + char name_buf[4]; + + xsnprintf (name_buf, sizeof (name_buf), "s%d", + dw_reg - FV_PSEUDO_REGNO_FIRST); + return user_reg_map_name_to_regnum (gdbarch, name_buf, + strlen (name_buf)); + } + + /* Others, unknown. */ + return -1; } /* Override interface for command: info register. */ diff --git a/gdb/csky-tdep.h b/gdb/csky-tdep.h index 4ff8a6b8613..4cfc0a5d086 100644 --- a/gdb/csky-tdep.h +++ b/gdb/csky-tdep.h @@ -108,6 +108,10 @@ enum csky_regnum /* For fr0~fr15, fr16~fr31, vr0~vr15 check. */ #define CSKY_FULL16_ONEHOT_VALUE 0xffff +/* Define for CSKY FV pseudo regs for dwarf regs. */ +#define FV_PSEUDO_REGNO_FIRST 74 +#define FV_PSEUDO_REGNO_LAST 201 + /* Number of processor registers w/o ICE registers. */ #define CSKY_NUM_REGS (CSKY_MAX_REGS - CSKY_CRBANK_NUM_REGS) -- 2.30.2