From d6309b914f4f201bc7065248c56870414d4b4712 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 1 Jun 2020 18:39:50 +0100 Subject: [PATCH] put RB in 2nd position (matching immediate) in ShiftRot Input Data --- src/soc/fu/shift_rot/pipe_data.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/fu/shift_rot/pipe_data.py b/src/soc/fu/shift_rot/pipe_data.py index 49b7b9c5..74d56bfe 100644 --- a/src/soc/fu/shift_rot/pipe_data.py +++ b/src/soc/fu/shift_rot/pipe_data.py @@ -9,21 +9,21 @@ from nmutil.dynamicpipe import SimpleHandshakeRedir class ShiftRotInputData(IntegerData): regspec = [('INT', 'a', '0:63'), - ('INT', 'rs', '0:63'), ('INT', 'rb', '0:63'), + ('INT', 'rs', '0:63'), ('XER', 'xer_ca', '34,45')] def __init__(self, pspec): super().__init__(pspec) self.a = Signal(64, reset_less=True) # RA - self.rs = Signal(64, reset_less=True) # RS self.rb = Signal(64, reset_less=True) # RB/immediate + self.rs = Signal(64, reset_less=True) # RS self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32 def __iter__(self): yield from super().__iter__() yield self.a - yield self.rs yield self.rb + yield self.rs yield self.xer_ca def eq(self, i): -- 2.30.2