From d633dd8428badb7271d0122e5aeab318673d913b Mon Sep 17 00:00:00 2001 From: Greta Yorsh Date: Fri, 5 Apr 2013 16:43:04 +0100 Subject: [PATCH] arm.md (subsi3_carryin): New pattern. 2013-04-05 Greta Yorsh * config/arm/arm.md (subsi3_carryin): New pattern. (subsi3_carryin_const): Likewise. (subsi3_carryin_compare,subsi3_carryin_compare_const): Likewise. (subsi3_carryin_shift,rsbsi3_carryin_shift): Likewise. From-SVN: r197520 --- gcc/ChangeLog | 9 ++++- gcc/config/arm/arm.md | 84 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 92 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6a591f638b8..5bc7e5eec8f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2013-04-05 Greta Yorsh + + * config/arm/arm.md (subsi3_carryin): New pattern. + (subsi3_carryin_const): Likewise. + (subsi3_carryin_compare,subsi3_carryin_compare_const): Likewise. + (subsi3_carryin_shift,rsbsi3_carryin_shift): Likewise. + 2013-04-05 Greta Yorsh * config/arm/arm.md (incscc,arm_incscc,decscc,arm_decscc): Delete. @@ -5,7 +12,7 @@ 2013-04-05 Greta Yorsh * config/arm/arm.md (addsi3_carryin_): Set attribute predicable. - (addsi3_carryin_alt2_,addsi3_carryin_shift_): Likewise. + (addsi3_carryin_alt2_,addsi3_carryin_shift_): Likewise. 2013-04-05 Kyrylo Tkachov diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 6dd6871b49a..3c1deaddddc 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -1015,6 +1015,90 @@ [(set_attr "conds" "set")] ) +(define_insn "*subsi3_carryin" + [(set (match_operand:SI 0 "s_register_operand" "=r,r") + (minus:SI (minus:SI (match_operand:SI 1 "reg_or_int_operand" "r,I") + (match_operand:SI 2 "s_register_operand" "r,r")) + (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] + "TARGET_32BIT" + "@ + sbc%?\\t%0, %1, %2 + rsc%?\\t%0, %2, %1" + [(set_attr "conds" "use") + (set_attr "arch" "*,a") + (set_attr "predicable" "yes")] +) + +(define_insn "*subsi3_carryin_const" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (minus:SI (plus:SI (match_operand:SI 1 "reg_or_int_operand" "r") + (match_operand:SI 2 "arm_not_operand" "K")) + (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] + "TARGET_32BIT" + "sbc\\t%0, %1, #%B2" + [(set_attr "conds" "use")] +) + +(define_insn "*subsi3_carryin_compare" + [(set (reg:CC CC_REGNUM) + (compare:CC (match_operand:SI 1 "s_register_operand" "r") + (match_operand:SI 2 "s_register_operand" "r"))) + (set (match_operand:SI 0 "s_register_operand" "=r") + (minus:SI (minus:SI (match_dup 1) + (match_dup 2)) + (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] + "TARGET_32BIT" + "sbcs\\t%0, %1, %2" + [(set_attr "conds" "set")] +) + +(define_insn "*subsi3_carryin_compare_const" + [(set (reg:CC CC_REGNUM) + (compare:CC (match_operand:SI 1 "reg_or_int_operand" "r") + (match_operand:SI 2 "arm_not_operand" "K"))) + (set (match_operand:SI 0 "s_register_operand" "=r") + (minus:SI (plus:SI (match_dup 1) + (match_dup 2)) + (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] + "TARGET_32BIT" + "sbcs\\t%0, %1, #%B2" + [(set_attr "conds" "set")] +) + +(define_insn "*subsi3_carryin_shift" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (minus:SI (minus:SI + (match_operand:SI 1 "s_register_operand" "r") + (match_operator:SI 2 "shift_operator" + [(match_operand:SI 3 "s_register_operand" "r") + (match_operand:SI 4 "reg_or_int_operand" "rM")])) + (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] + "TARGET_32BIT" + "sbc%?\\t%0, %1, %3%S2" + [(set_attr "conds" "use") + (set_attr "predicable" "yes") + (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") + (const_string "alu_shift") + (const_string "alu_shift_reg")))] +) + +(define_insn "*rsbsi3_carryin_shift" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (minus:SI (minus:SI + (match_operator:SI 2 "shift_operator" + [(match_operand:SI 3 "s_register_operand" "r") + (match_operand:SI 4 "reg_or_int_operand" "rM")]) + (match_operand:SI 1 "s_register_operand" "r")) + (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] + "TARGET_ARM" + "rsc%?\\t%0, %1, %3%S2" + [(set_attr "conds" "use") + (set_attr "predicable" "yes") + (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") + (const_string "alu_shift") + (const_string "alu_shift_reg")))] +) + ; transform ((x << y) - 1) to ~(~(x-1) << y) Where X is a constant. (define_split [(set (match_operand:SI 0 "s_register_operand" "") -- 2.30.2