From d64bf3662989d5f04da0657e154ccea5124e2872 Mon Sep 17 00:00:00 2001 From: Konstantinos Margaritis Date: Wed, 27 Jul 2022 11:01:37 +0000 Subject: [PATCH] Add fishmv instruction (bug #887) --- openpower/isa/av.mdwn | 17 ++++++++++++ openpower/isatables/minor_22.csv | 1 + src/openpower/decoder/isa/caller.py | 4 ++- .../decoder/isa/test_caller_fmvis.py | 2 +- src/openpower/decoder/power_enums.py | 2 ++ src/openpower/sv/trans/svp64.py | 26 ++++++++++++++++++- src/openpower/test/alu/fmvis_cases.py | 15 +++++++++++ 7 files changed, 64 insertions(+), 3 deletions(-) diff --git a/openpower/isa/av.mdwn b/openpower/isa/av.mdwn index 0eb48f8e..1347adcc 100644 --- a/openpower/isa/av.mdwn +++ b/openpower/isa/av.mdwn @@ -221,3 +221,20 @@ Pseudo-code: Special Registers Altered: None + +# Float Replace Lower-Half Single, Immediate + +DX-Form + +* fishmv FRS,D + +Pseudo-code: + + LH <- FRS[0:15] + fp32 <- LH || d0 || d1 || d2 + n <- DOUBLE(fp32) + FRS <- LH || n[16:63] + +Special Registers Altered: + + None diff --git a/openpower/isatables/minor_22.csv b/openpower/isatables/minor_22.csv index 4f76782a..a0207c06 100644 --- a/openpower/isatables/minor_22.csv +++ b/openpower/isatables/minor_22.csv @@ -20,3 +20,4 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou 0110001110-,ALU,OP_CPROP,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,cprop,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg ------10001,ALU,OP_BMASK,RA,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,bmask,BM2,,1,unofficial until submitted and approved/renumbered by the opf isa wg -----00011-,ALU,OP_FMVIS,NONE,CONST_UI,NONE,FRS,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,fmvis,DX,,1,unofficial until submitted and approved/renumbered by the opf isa wg +-----01011-,ALU,OP_FISHMV,FRS,CONST_UI,NONE,FRS,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,fishmv,DX,,1,unofficial until submitted and approved/renumbered by the opf isa wg diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index c6096b25..13b3fc03 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -1236,7 +1236,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers): 'setvl', 'svindex', 'svremap', 'svstep', 'svshape', 'grev', 'ternlogi', 'bmask', 'cprop', 'absdu', 'absds', 'absdacs', 'absdacu', 'avgadd', - 'fmvis', + 'fmvis', 'fishmv', ]: illegal = False ins_name = dotstrp @@ -1332,7 +1332,9 @@ class ISACaller(ISACallerHelper, ISAFPHelpers): # main input registers (RT, RA ...) inputs = [] for name in input_names: + print("name", name) regval = (yield from self.get_input(name)) + print("regval", regval) inputs.append(regval) # arrrrgh, awful hack, to get _RT into namespace diff --git a/src/openpower/decoder/isa/test_caller_fmvis.py b/src/openpower/decoder/isa/test_caller_fmvis.py index ce44d033..63e923d6 100644 --- a/src/openpower/decoder/isa/test_caller_fmvis.py +++ b/src/openpower/decoder/isa/test_caller_fmvis.py @@ -21,7 +21,7 @@ if __name__ == "__main__": sys.argv = sys.argv[:1] if not testing: - testing = ['fmvis'] + testing = ['fmvis', 'fishmv'] unittest.main(exit=False) suite = unittest.TestSuite() diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py index a5e92880..3c8f9afd 100644 --- a/src/openpower/decoder/power_enums.py +++ b/src/openpower/decoder/power_enums.py @@ -295,6 +295,7 @@ _insns = [ "fmr", "fabs", "fnabs", "fneg", "fcpsgn", # FP move/abs/neg "fsins", "fcoss", # FP SIN/COS "fmvis", # FP load immediate + "fishmv", # Float Replace Lower-Half Single, Immediate 'grev', 'grev.', 'grevi', 'grevi.', 'grevw', 'grevw.', 'grevwi', 'grevwi.', "hrfid", "icbi", "icbt", "isel", "isync", @@ -463,6 +464,7 @@ class MicrOp(Enum): OP_BMASK = 94 OP_SVINDEX = 95 OP_FMVIS = 96 + OP_FISHMV = 97 @unique diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index a285d1a3..6c3e032f 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -339,7 +339,6 @@ def fmvis(fields): # | PO | FRS | d1 | d0 | XO |d2 | PO = 22 XO = 0b00011 - Rc = 0 (FRS, imm) = fields # first split imm into d1, d0 and d2. sigh d2 = (imm & 1) # LSB (0) @@ -355,6 +354,30 @@ def fmvis(fields): ) +def fishmv(fields): + # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG + # V3.0B 1.6.6 DX-FORM + # |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |26|27 |31 | + # | PO | FRS | d1 | d0 | XO |d2 | + PO = 22 + XO = 0b01011 + (FRS, imm) = fields + # first split imm into d1, d0 and d2. sigh + d2 = (imm & 1) # LSB (0) + d1 = (imm >> 1) & 0b11111 # bits 1-5 + d0 = (imm >> 5) # MSBs 6-15 + print("imm", hex(imm)) + print("d0 d1 d2", hex(d0), hex(d1), hex(d2)) + return instruction( + (PO , 0 , 5), + (FRS, 6 , 10), + (d1, 11, 15), + (d0, 16, 26), + (XO , 27, 30), + (d2 , 31, 31), + ) + + CUSTOM_INSNS = {} for (name, hook) in ( ("setvl", setvl), @@ -370,6 +393,7 @@ CUSTOM_INSNS["svshape"] = svshape CUSTOM_INSNS["svindex"] = svindex CUSTOM_INSNS["svremap"] = svremap CUSTOM_INSNS["fmvis"] = fmvis +CUSTOM_INSNS["fishmv"] = fishmv for (name, imm, wide) in ( ("grev", False, False), diff --git a/src/openpower/test/alu/fmvis_cases.py b/src/openpower/test/alu/fmvis_cases.py index e698ed36..2ddaf207 100644 --- a/src/openpower/test/alu/fmvis_cases.py +++ b/src/openpower/test/alu/fmvis_cases.py @@ -26,3 +26,18 @@ class FMVISTestCase(TestAccumulatorBase): e = ExpectedState(pc=0xc, # 3 instructions so 3x4=0xc fp_regs=expected_fprs) # expected results self.add_case(Program(lst, bigendian), expected=e) + + def case_1_fishmv(self): + + lst = SVP64Asm(["fmvis 3, 0x4049", # 1st half of 3.14159 in FP32 form + "fishmv 3, 0x0FD0", # 2nd half of 3.14159 in FP32 form + "fmvis 5, 0x3F80", # 1st half of 1.00195 in FP32 form + "fishmv 5, 0x4000", # 2nd half of 1.00195 in FP32 form + ]) + lst = list(lst) + + expected_fprs = [0] * 32 + expected_fprs[3] = 0x400921fa00000000 # 3.14159 in FP64 form + expected_fprs[5] = 0x3ff0080000000000 # 1.00195 in FP64 form + e = ExpectedState(pc=0x10, fp_regs=expected_fprs) + self.add_case(Program(lst, bigendian), expected=e) -- 2.30.2