From d66f38c7dc4a8a2531f380971c4d4d58579ca878 Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 14 Sep 2022 23:20:32 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls001.mdwn | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index 37229471b..234b3f4b1 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -389,7 +389,7 @@ is concerned, remains expressed as *Scalar assembler*.[^autovec] Whilst Mitch Alsup's VVM advocates auto-vectorisation and is limited in its ability to call functions, Simple-V's Vertical-First provides explicit control over the -parallelism ("hphint") and also allows for full state to be stored/restored +parallelism ("hphint")[^hphint] and also allows for full state to be stored/restored (SVLR combined with LR), permitting full function calls to be made. Simple-V Vertical-First Looping requires an explicit instruction to @@ -852,3 +852,4 @@ operations. [^futurevsx]: A future version or other Stakeholder *may* wish to drop Simple-V onto VSX: this would be a separate RFC [^vsx256]: imagine a hypothetical future VSX-256 using the exact same instructions as VSX. the binary incompatibility introducrd would catastrophically **and retroactively** damage existing IBM POWER8,9,10 hardware's reputation and that of Power ISA overall. [^autovec]: Compiler auto-vectorisation for best exploitation of SIMD and Vector ISAs on Scalar programming languages (c, c++) is an Indusstry-wide known-hard decades-long problem. Cross-reference the number of hand-optimised assembler algorithms. +[^hphint]: intended for use when the compiler has determined the extent of Memory or register aliases in loops: `a[i] += a[i+4]` would necessitate a Vertical-First hphint of 4 -- 2.30.2