From d677c93750bfc705f408a801727dc735be39ec9d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 29 Sep 2018 03:49:49 +0100 Subject: [PATCH] add 8 CSRs for registers and predication each each CSR contains 2 16-bit entries and is a CAM based on register as key (5-bit) and target-register as value (6-bit) so that a 5-bit RS1-3/RD can actually reach 64 actual registers, and *3-bit C instructions can as well* --- riscv/encoding.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/riscv/encoding.h b/riscv/encoding.h index f06e785..d7bb800 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -892,6 +892,22 @@ #define CSR_MHPMEVENT29 0x33d #define CSR_MHPMEVENT30 0x33e #define CSR_MHPMEVENT31 0x33f +#define CSR_SVREGCFG0 0xcc0 +#define CSR_SVREGCFG1 0xcc1 +#define CSR_SVREGCFG2 0xcc2 +#define CSR_SVREGCFG3 0xcc3 +#define CSR_SVREGCFG4 0xcc4 +#define CSR_SVREGCFG5 0xcc5 +#define CSR_SVREGCFG6 0xcc6 +#define CSR_SVREGCFG7 0xcc7 +#define CSR_SVPREDCFG0 0xcc8 +#define CSR_SVPREDCFG1 0xcc9 +#define CSR_SVPREDCFG2 0xcca +#define CSR_SVPREDCFG3 0xccb +#define CSR_SVPREDCFG4 0xccc +#define CSR_SVPREDCFG5 0xccd +#define CSR_SVPREDCFG6 0xcce +#define CSR_SVPREDCFG7 0xccf #define CSR_SVVL 0xcf0 #define CSR_SVREALVL 0xcf1 #define CSR_SVMVL 0xcf2 -- 2.30.2