From d6af7e5456b17bab0f542738b17c73d1e66e9160 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 21 May 2020 12:45:33 +0100 Subject: [PATCH] move FU IntegerData to directory below --- src/soc/fu/alu/pipe_data.py | 17 +---------------- src/soc/fu/branch/pipe_data.py | 2 +- src/soc/fu/cr/pipe_data.py | 2 +- src/soc/fu/logical/pipe_data.py | 3 ++- src/soc/fu/logical/test/test_pipe_caller.py | 3 +-- src/soc/fu/pipe_data.py | 17 +++++++++++++++++ src/soc/fu/shift_rot/pipe_data.py | 3 ++- src/soc/fu/trap/pipe_data.py | 2 +- 8 files changed, 26 insertions(+), 23 deletions(-) create mode 100644 src/soc/fu/pipe_data.py diff --git a/src/soc/fu/alu/pipe_data.py b/src/soc/fu/alu/pipe_data.py index 32e2944a..768d6a44 100644 --- a/src/soc/fu/alu/pipe_data.py +++ b/src/soc/fu/alu/pipe_data.py @@ -1,26 +1,11 @@ from nmigen import Signal, Const from nmutil.dynamicpipe import SimpleHandshakeRedir from soc.fu.alu.alu_input_record import CompALUOpSubset +from soc.fu.pipe_data import IntegerData from ieee754.fpcommon.getop import FPPipeContext from soc.decoder.power_decoder2 import Data -class IntegerData: - - def __init__(self, pspec): - self.ctx = FPPipeContext(pspec) - self.muxid = self.ctx.muxid - - def __iter__(self): - yield from self.ctx - - def eq(self, i): - return [self.ctx.eq(i.ctx)] - - def ports(self): - return self.ctx.ports() - - class ALUInputData(IntegerData): regspec = [('INT', 'a', '0:63'), ('INT', 'b', '0:63'), diff --git a/src/soc/fu/branch/pipe_data.py b/src/soc/fu/branch/pipe_data.py index 13179c8f..80b601e1 100644 --- a/src/soc/fu/branch/pipe_data.py +++ b/src/soc/fu/branch/pipe_data.py @@ -26,7 +26,7 @@ from nmigen import Signal, Const from ieee754.fpcommon.getop import FPPipeContext from soc.decoder.power_decoder2 import Data -from soc.fu.alu.pipe_data import IntegerData +from soc.fu.pipe_data import IntegerData from nmutil.dynamicpipe import SimpleHandshakeRedir from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace diff --git a/src/soc/fu/cr/pipe_data.py b/src/soc/fu/cr/pipe_data.py index a6cd835e..7a9e4422 100644 --- a/src/soc/fu/cr/pipe_data.py +++ b/src/soc/fu/cr/pipe_data.py @@ -1,6 +1,6 @@ from nmigen import Signal, Const from ieee754.fpcommon.getop import FPPipeContext -from soc.fu.alu.pipe_data import IntegerData +from soc.fu.pipe_data import IntegerData from nmutil.dynamicpipe import SimpleHandshakeRedir from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace diff --git a/src/soc/fu/logical/pipe_data.py b/src/soc/fu/logical/pipe_data.py index 256317cb..eb012713 100644 --- a/src/soc/fu/logical/pipe_data.py +++ b/src/soc/fu/logical/pipe_data.py @@ -1,6 +1,7 @@ from nmigen import Signal, Const from ieee754.fpcommon.getop import FPPipeContext -from soc.fu.alu.pipe_data import IntegerData, ALUOutputData +from soc.fu.pipe_data import IntegerData +from soc.fu.alu.pipe_data import ALUOutputData from nmutil.dynamicpipe import SimpleHandshakeRedir from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py index c14f6a08..a676e8f6 100644 --- a/src/soc/fu/logical/test/test_pipe_caller.py +++ b/src/soc/fu/logical/test/test_pipe_caller.py @@ -11,9 +11,8 @@ from soc.decoder.selectable_int import SelectableInt from soc.simulator.program import Program from soc.decoder.isa.all import ISA - from soc.fu.logical.pipeline import LogicalBasePipe -from soc.fu.alu.pipe_data import LogicalPipeSpec +from soc.fu.logical.pipe_data import LogicalPipeSpec import random diff --git a/src/soc/fu/pipe_data.py b/src/soc/fu/pipe_data.py new file mode 100644 index 00000000..764de09f --- /dev/null +++ b/src/soc/fu/pipe_data.py @@ -0,0 +1,17 @@ +from ieee754.fpcommon.getop import FPPipeContext + + +class IntegerData: + + def __init__(self, pspec): + self.ctx = FPPipeContext(pspec) + self.muxid = self.ctx.muxid + + def __iter__(self): + yield from self.ctx + + def eq(self, i): + return [self.ctx.eq(i.ctx)] + + def ports(self): + return self.ctx.ports() diff --git a/src/soc/fu/shift_rot/pipe_data.py b/src/soc/fu/shift_rot/pipe_data.py index 39370522..29f07efc 100644 --- a/src/soc/fu/shift_rot/pipe_data.py +++ b/src/soc/fu/shift_rot/pipe_data.py @@ -2,7 +2,8 @@ from nmigen import Signal, Const from nmutil.dynamicpipe import SimpleHandshakeRedir from soc.fu.alu.alu_input_record import CompALUOpSubset from ieee754.fpcommon.getop import FPPipeContext -from soc.fu.alu.pipe_data import ALUOutputData, IntegerData +from soc.fu.pipe_data import IntegerData +from soc.fu.alu.pipe_data import ALUOutputData from nmutil.dynamicpipe import SimpleHandshakeRedir diff --git a/src/soc/fu/trap/pipe_data.py b/src/soc/fu/trap/pipe_data.py index af0e9d7a..de930da3 100644 --- a/src/soc/fu/trap/pipe_data.py +++ b/src/soc/fu/trap/pipe_data.py @@ -1,6 +1,6 @@ from nmigen import Signal, Const from ieee754.fpcommon.getop import FPPipeContext -from soc.fu.alu.pipe_data import IntegerData +from soc.fu.pipe_data import IntegerData from soc.decoder.power_decoder2 import Data from nmutil.dynamicpipe import SimpleHandshakeRedir from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace -- 2.30.2