From d6b0819e4c072265a67a4a31475a9b5f983ab766 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 21 Mar 2020 19:36:31 +0100 Subject: [PATCH] integration/soc/add_ethernet: add name parameter (defaults to ethmac). --- litex/soc/integration/soc.py | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index a070fbb3..4922ece5 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1037,19 +1037,20 @@ class LiteXSoC(SoC): base_address = self.bus.regions["main_ram"].origin) # Add Ethernet --------------------------------------------------------------------------------- - def add_ethernet(self, phy): + def add_ethernet(self, name="ethmac", phy=None): # Imports from liteeth.mac import LiteEthMAC # MAC - self.submodules.ethmac = LiteEthMAC( + ethmac = LiteEthMAC( phy = phy, dw = 32, interface = "wishbone", endianness = self.cpu.endianness) - ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None), size=0x2000, cached=False) - self.bus.add_slave(name="ethmac", slave=self.ethmac.bus, region=ethmac_region) - self.add_csr("ethmac") - self.add_interrupt("ethmac") + setattr(self.submodules, name, ethmac) + ethmac_region = SoCRegion(origin=self.mem_map.get(name, None), size=0x2000, cached=False) + self.bus.add_slave(name=name, slave=ethmac.bus, region=ethmac_region) + self.add_csr(name) + self.add_interrupt(name) # Timing constraints if hasattr(phy, "crg"): eth_rx_clk = phy.crg.cd_eth_rx.clk -- 2.30.2