From d6c19858faf09f9ca6d2a31370f87187b4f16358 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Thu, 9 Apr 2015 19:17:02 -0600 Subject: [PATCH] s6ddrphy: redo phase_sel, get rid of CLOCK_DEDICATED_ROUTE --- misoclib/mem/sdram/phy/s6ddrphy.py | 11 +++++++---- targets/mlabs_video.py | 2 -- targets/pipistrello.py | 3 --- 3 files changed, 7 insertions(+), 9 deletions(-) diff --git a/misoclib/mem/sdram/phy/s6ddrphy.py b/misoclib/mem/sdram/phy/s6ddrphy.py index 1f505df6..b70260e8 100644 --- a/misoclib/mem/sdram/phy/s6ddrphy.py +++ b/misoclib/mem/sdram/phy/s6ddrphy.py @@ -69,15 +69,18 @@ class S6DDRPHY(Module): # sys_clk ----____----____ # phase_sel(nphases=2) 0 1 0 1 Half Rate phase_sel = Signal(log2_int(nphases)) - sys_clk_d = Signal() + phase_half = Signal.like(phase_sel) + phase_sys = Signal.like(phase_half) + + sd_sys += phase_sys.eq(phase_half) sd_sdram_half += [ - If(sys_clk & ~sys_clk_d, - phase_sel.eq(0) + If(phase_half == phase_sys, + phase_sel.eq(0), ).Else( phase_sel.eq(phase_sel+1) ), - sys_clk_d.eq(sys_clk) + phase_half.eq(phase_half+1), ] # register dfi cmds on half_rate clk diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py index c918686e..f8946069 100644 --- a/targets/mlabs_video.py +++ b/targets/mlabs_video.py @@ -61,8 +61,6 @@ class BaseSoC(SDRAMSoC): platform.add_platform_command(""" INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2"; INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3"; - -PIN "mxcrg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE; """) platform.add_source_dir(os.path.join("misoclib", "others", "mxcrg")) diff --git a/targets/pipistrello.py b/targets/pipistrello.py index d656b6a8..94cb2291 100644 --- a/targets/pipistrello.py +++ b/targets/pipistrello.py @@ -110,9 +110,6 @@ class BaseSoC(SDRAMSoC): self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb), self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb), ] - platform.add_platform_command(""" - PIN "BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE; - """) self.register_sdram_phy(self.ddrphy) if not self.integrated_rom_size: -- 2.30.2