From d6c2c2270b0688ae3e8950b71e7a6f92bf474d6b Mon Sep 17 00:00:00 2001 From: Alain D D Williams Date: Fri, 21 Aug 2020 17:25:28 +0100 Subject: [PATCH] Recent work --- .../powerpc-add/build/Makefile | 68 ------ libresoc-isa-manual/powerpc-add/src/intro.tex | 217 ------------------ .../powerpc-add/src/power-spec.bib | 6 - .../powerpc-add/src/power-spec.tex | 93 -------- .../powerpc-add/src/preamble.tex | 148 ------------ .../powerpc-add/src/preface.tex | 5 - powerpc-add/.gitignore | 1 + powerpc-add/src/atomics.tex | 2 + powerpc-add/src/fp16.tex | 2 + powerpc-add/src/glossary.tex | 107 ++++++++- powerpc-add/src/intro.tex | 2 +- powerpc-add/src/isa_op_protocol.tex | 2 + powerpc-add/src/isamux.tex | 5 +- powerpc-add/src/power-spec.tex | 5 + powerpc-add/src/varenc.tex | 2 + 15 files changed, 122 insertions(+), 543 deletions(-) delete mode 100644 libresoc-isa-manual/powerpc-add/build/Makefile delete mode 100644 libresoc-isa-manual/powerpc-add/src/intro.tex delete mode 100644 libresoc-isa-manual/powerpc-add/src/power-spec.bib delete mode 100644 libresoc-isa-manual/powerpc-add/src/power-spec.tex delete mode 100644 libresoc-isa-manual/powerpc-add/src/preamble.tex delete mode 100644 libresoc-isa-manual/powerpc-add/src/preface.tex create mode 100644 powerpc-add/src/atomics.tex create mode 100644 powerpc-add/src/fp16.tex create mode 100644 powerpc-add/src/isa_op_protocol.tex create mode 100644 powerpc-add/src/varenc.tex diff --git a/libresoc-isa-manual/powerpc-add/build/Makefile b/libresoc-isa-manual/powerpc-add/build/Makefile deleted file mode 100644 index 0a534fd..0000000 --- a/libresoc-isa-manual/powerpc-add/build/Makefile +++ /dev/null @@ -1,68 +0,0 @@ -#======================================================================= -# Makefile for generating LaTeX documents -#----------------------------------------------------------------------- -# -# This is a simple makefile for generating LaTeX documents. It will -# run bibtex, generate eps from xfig figures, and make pdfs. The -# makefile supports builds in non-source directories: just make a -# build directory, copy the makefile there, and change the srcdir -# variable accordingly. -# -# Note that the makefile assumes that the default dvips/ps2pdfwr -# commands "do the right thing" for fonts in pdfs. This is true on -# Athena/Linux and Fedora Core but is not true for older redhat installs ... -# -# At a minimum you should just change the main variable to be -# the basename of your toplevel tex file. If you use a bibliography -# then you should set the bibfile variable to be the name of your -# .bib file (assumed to be in the source directory). -# - -srcdir = ../src - -docs_with_bib = power-spec -docs_without_bib = - -srcs = $(wildcard $(srcdir)/*.tex) -figs = $(wildcard $(srcdir)/figs/*) -bibs = $(srcdir)/power-spec.bib - -#======================================================================= -# You shouldn't need to change anything below this -#======================================================================= - -PDFLATEX := TEXINPUTS=$(srcdir): pdflatex -interaction=nonstopmode -halt-on-error -BIBTEX := BIBINPUTS=$(srcdir): bibtex - -default : pdf - -#------------------------------------------------------------ -# PDF - -pdfs_with_bib = $(addsuffix .pdf, $(docs_with_bib)) -pdfs_without_bib = $(addsuffix .pdf, $(docs_without_bib)) -pdfs = $(pdfs_with_bib) $(pdfs_without_bib) - -pdf : $(pdfs) -.PHONY: pdf open - -open: $(pdfs) - open $(pdfs) - -$(pdfs_with_bib): %.pdf: $(srcdir)/%.tex $(srcs) $(figs) $(bibs) - $(PDFLATEX) $* - $(BIBTEX) $* - $(PDFLATEX) $* - $(PDFLATEX) $* - -$(pdfs_without_bib): %.pdf: $(srcdir)/%.tex $(srcs) $(figs) - $(PDFLATEX) $* - $(PDFLATEX) $* - -junk += $(pdfs) *.aux *.log *.bbl *.blg *.toc *.out - -#------------------------------------------------------------ -# Other Targets - -clean : - rm -rf $(junk) *~ \#* diff --git a/libresoc-isa-manual/powerpc-add/src/intro.tex b/libresoc-isa-manual/powerpc-add/src/intro.tex deleted file mode 100644 index 2f98bcf..0000000 --- a/libresoc-isa-manual/powerpc-add/src/intro.tex +++ /dev/null @@ -1,217 +0,0 @@ -% -\chapter{Introduction} - -\section{Why has Libre-SOC chosen PowerPC ?} - -For a hybrid CPU-VPU-GPU, intended for mass-volume adoption in tablets, -netbooks, chromebooks and industrial embedded (SBC) systems, our choice was -between Nyuzi, MIAOW, RISC-V, PowerPC, MIPS and OpenRISC. - -Of all the options, the PowerPC architecture is more complete and far more -mature. It also has a deeper adoption by Linux distributions. - -Following IBM's release of the Power Architecture instruction set to the Linux -Foundation in August 2019 the barrier to using it is no more than that of using -RISC-V. We are encouraged that the OpenPOWER Foundation is supportive of what -we are doing and helping, e.g by putting us in touch with people who can help -us. - -\subsection{Summary} - -\vspace{-0.1in} -\begin{itemize} -\parskip 0pt -\itemsep 1pt - -\item - We propose the standardisation of the way that the PowerPC Instruction Set - Architecture (PPC ISA) is extended, enabling many different flavours within a - well supported family to co-exist, long-term, without conflict, right across - the board. - -\item - - This is about more than just our project. Our proposals will facilitate the - use of PPC in novel or niche applications without breaking the PPC ISA into - incompatible islands. - -\item - - PPC will gain a competitive market advantage by removing the need for - separate VPU or GPU functions in RTL or ASICs thus enabling lower cost - systems. Libre-SOC's project is to extend the PPC to integrate the GPU and - VPU functionality directly as part of the PPC ISA (example: Broadcom - VideoCore IV being based around extensions to an ARC core). - -\item - - Libre-SOC's extensions will be easily adopted, as the standard GNU/Linux - distributions will very deliberately run unmodified on our ISA, including - full compatibility with illegal instruction trap requirements. - -\end{itemize} - - -\subsection{One CPU multiple ISAs} - -This is a quick overview of the way that we would like to add changes that we -are proposing to the PowerPC instruction set (ISA). It is based on a Open -Standardisation of the way that existing "mode switches", already found in the -POWER instruction set, are added: - -\begin{itemize} -\parskip 0pt -\itemsep 1pt - -\item - - FPSCR's "NI" bit, setting non-IEEE754 FP mode - -\item - - MSR's "LE" bit (and associated HILE bit), setting little-endian mode - -\item - - MSR's "SF" bit, setting either 32-bit or 64-bit mode - -\item - - PCR's "compatibility" bits 60-62, V2.05 V2.06 V2.07 mode - -\end{itemize} - -[It is well-noted that unless each "mode switch" bit is set, any alternative -(additional) instructions (and functionality) are completely inaccessible, and -will result in "illegal instruction" traps being thrown. This is recognised as -being critically important.] - -These bits effectively create multiple, incompatible run-time switchable ISAs -within one CPU. They are selectable for the needs of the individual program (or -OS) being run. - -All of these bits are set by an instruction, that, once set, radically changes -the entire behaviour and characteristics of subsequent instructions. - -With these (and other) long-established precedents already in POWER, there is -therefore essentially conceptually nothing new about what we propose: we simply -seek that the process by which such "switching" is added is formalised and -standardised, such that we (and others, including IBM itself) have a clear, -well-defined standards-non-disruptive, atomic and non-intrusive path to extend -the POWER ISA for use in markets that it presently cannot enter. - -We advocate that some of "mode-setting" (escape-sequencing) bits be binary -encoded, some unary encoded, and that some space marked for "offical" use, some -"experimental", some "custom" and some "reserved". The available space in a -suitably-chosen SPR to be formalised, and recommend the OpenPOWER Foundation be -given the IANA-like role in atomically allocating mode bits. - -The IANA-like atomic role ensures that new PCR mode bits are allocated -world-wide unique. In combination with a mandatory illegal instruction -exception to be thrown on any system not supporting any given mode, the -opportunity exists for all systems to trap and emulate all other systems and -thus retain some semblance of interoperability. (Contrast this with either -allocating the same mode bit(s) to two (or more) designers, or not making -illegal exceptions mandatory: binary interoperability becomes unachievable and -the result is irrevocable damage to POWER's reputation.) - -We also advocate to consider reserving some bits as a "countdown" where the new -mode will be enabled only for a certain number of instructions. This avoids an -explicit need to "flip back", reducing binary code size. Note that it is not a -good idea to let the counter cross a branch or other change in PC (and to throw -illegal instruction trap if attempted). However traps and exceptions themselves -will need to save (and restore) the countdown, just as the rest of the PCR and -other modeswitching bits need to be saved. - -Instructions that we need to add, which are a normal part of GPUs, include -ATAN2, LOG, NORMALISE, YUV2RGB, Khronos Compliance FP mode (different from both -IEEE754 and "NI" mode), and many more. Many of these may turn out to be useful -in a wider context: they however need to be fully isolated behind -"mode-setting" before being in any way considered for Standards-track formal -adoption. - -Some mode-setting instructions are privileged, i.e can only be set by the -kernel (e.g 32 or 64 bit mode). Most of the escape sequences that we propose -will be (have to be) usable without the need for an expensive system call -overhead (because some of the instructions needed will be in extremely tight -inner loops). - -\subsection{About Libre-SOC Commercial Project} - -The Libre-SOC Commercial Product is a hybrid GPU-GPU-VPU intended for -mass-volume production. There is no separate GPU, because the CPU is the GPU. -There is no separate VPU, because the CPU is the GPU. There is not even a -separate pipeline: the CPU pipelines are the GPU and VPU pipelines. - -Closest equivalents include the ARC core (which has VPU extensions and 3D -extensions in the form of Broadcom's VideoCore IV) and the ICubeCorp IC3128. -Both are considered "hybrid" CPU-GPU-VPU processors. - -"Normal" Commercial GPUs are entirely separate processors. The development cost -and complexity purely in terms of Software Drivers alone is immense. We reject -that approach (and as a small team we do not have the resources anyway). - -With the project being Libre - not proprietary and secretive and never to be -published, ever - it is no good having the extensions as "custom" because -"custom" is specifically for the cases where the augmented toolchain is never, -under any circumstances, published and made public by the proprietary company -(and would never be accepted upstream anyway). For business commercial reasons, -Libre-SOC is the total opposite of this proprietary, secretive approach. - -Therefore, to meet our business objectives: - -\begin{itemize} -\parskip 0pt -\itemsep 1pt - -\item - - As shown from Nyuzi and Larrabee, although ideally suited to high - performance compute tasks, a "traditional" general-purpose full - IEEE754-compliant Vector ISA (such as that in POWER9) is not an adequate - basis for a commercially competitive GPU. Nyuzi's conclusion is that using - such general-purpose Vector ISAs results in reaching only 25% performance - (or requiring 4-fold increase in power consumption) to achieve par with - current commercial-grade GPUs. - -\item - - We are not going the "traditional" (separate custom GPU) route because it - is not practical for a new team to design hardware and spend 8+ man-years - on massively complex inter-processor driver development as well - -\item - - We cannot meet our objectives with a "custom extension" because the - financial burden on our team to maintain a total hard fork of not just - toolchains, but also entire GNU/Linux Distros, is highly undesirable, and - completely impractical (we know for certain that Redhat would strongly - object to any efforts to hard-fork Fedora) - -\item - - We could invent our own custom GPU instruction set (or use and extend an - existing one, to save a man-decade on toolchain development) however even - to switch over to that "Dual ISA" GPU instruction set in the next clock - cycle still requires a PCR modeswitch bit in order to avoid needing a full - Inter-Processor Bus Architecture like on "traditional" GPUs. - -\item - - If extending any instruction set, rather than have a Dual ISA (which needs - the PCR modeswitch bit to access it) we would rather extend POWER. - -\item - - We cannot "go ahead anyway" because to do so would be highly irresponsible - and cause massive disruption to the POWER community. - -\end{itemize} - -With all impractical options eliminated the only remaining responsible option -is to extend the POWER ISA in an atomically-managed (IANA-style) formal -fashion, whilst (critically and absolutely essentially) always providing a PCR -compatibility mode that is fully POWER compliant, including all illegal -instruction traps. - - diff --git a/libresoc-isa-manual/powerpc-add/src/power-spec.bib b/libresoc-isa-manual/powerpc-add/src/power-spec.bib deleted file mode 100644 index cbdab86..0000000 --- a/libresoc-isa-manual/powerpc-add/src/power-spec.bib +++ /dev/null @@ -1,6 +0,0 @@ -@Misc{foo-bar, - title = "A dummy bib entry to keep LaTeX happy", - publisher = {"Libre-SOC"}, - year = 2020 -} - diff --git a/libresoc-isa-manual/powerpc-add/src/power-spec.tex b/libresoc-isa-manual/powerpc-add/src/power-spec.tex deleted file mode 100644 index 55a1c33..0000000 --- a/libresoc-isa-manual/powerpc-add/src/power-spec.tex +++ /dev/null @@ -1,93 +0,0 @@ -% -%======================================================================= -% power-spec.tex -%----------------------------------------------------------------------- - -\documentclass[twoside,11pt]{book} - -% Fix copy/pasting of ligatures in Acrobat -\input{glyphtounicode.tex} -\pdfgentounicode=1 % - -\input{preamble} - -\newcommand{\specrev}{\mbox{20200813-{\em draft}}} -\newcommand{\specmonthyear}{\mbox{August 2020}} - -\begin{document} - -\title{\vspace{-0.7in}\Large {\bf Additions to The PowerPC Instruction Set Manual} \\ - \large {\bf Libre-SOC Extensions} \\ - Document Version \specrev - \vspace{-0.1in}} - -\author{Editor: Alain D D Williams$^{1}$ \\ - $^{1}$Parliament Hill Computers Ltd, \\ - {\tt addw@phcomp.co.uk} \\ - \today -} -\date{} -\maketitle - -Contributors to all versions of the spec in -alphabetical order (please contact editors to suggest -corrections): -Luke Kenneth Casson Leighton, Jacob R Lifshay, Alain D D Williams - -This document is released under a Creative Commons Attribution 4.0 -International License. - -Please cite as: ``The PowerPC Instruction Set Additions, Document Version \specrev'', Editors -Alain Williams, Libre-SOC, \specmonthyear. - - -\markboth{Volume I: PowerPC ISAMUX \specrev} -{Volume I: PowerPC ISAMUX \specrev} -\thispagestyle{empty} - -\frontmatter - -\input{preface} - -{\hypersetup{linktoc=all,hidelinks} -\tableofcontents -} - -\mainmatter - -\input{intro} -% \input{rv32} -% \input{zifencei} -% \input{rv32e} -% \input{rv64} -% \input{rv128} -% \input{m} -% \input{a} -% \input{csr} -% \input{counters} -% \input{f} -% \input{d} -% \input{q} -% \input{rvwmo} -% \input{l} -% \input{c} -% \input{b} -% \input{j} -% \input{t} -% \input{p} -% \input{v} -% \input{zam} -% \input{ztso} -% \input{gmaps} -% \input{assembly} -% \input{extensions} -% \input{naming} -% \input{history} -% -% \appendix -% \input{memory} - -\bibliographystyle{plain} -\bibliography{power-spec} - -\end{document} diff --git a/libresoc-isa-manual/powerpc-add/src/preamble.tex b/libresoc-isa-manual/powerpc-add/src/preamble.tex deleted file mode 100644 index 89cbd2d..0000000 --- a/libresoc-isa-manual/powerpc-add/src/preamble.tex +++ /dev/null @@ -1,148 +0,0 @@ -% Package includes - -\usepackage{graphicx} -\usepackage{geometry} -\usepackage{array} -\usepackage{colortbl} -\usepackage[svgnames]{xcolor} - -\usepackage[colorlinks,citecolor=Navy,linkcolor=Navy]{hyperref} -\usepackage{placeins} -\usepackage{longtable} -\usepackage{multirow} -\usepackage{float} -\usepackage{listings} -\usepackage{comment} -\usepackage{enumitem} -\usepackage{verbatimbox} -\usepackage{amsmath} - -\usepackage[olditem,oldenum]{paralist} - -% Setup margins - -\setlength{\topmargin}{-0.5in} -\setlength{\textheight}{9in} -\setlength{\oddsidemargin}{0in} -\setlength{\evensidemargin}{0in} -\setlength{\textwidth}{6.5in} - -% Useful macros - -\newcommand{\note}[1]{{\bf [ NOTE: #1 ]}} -\newcommand{\fixme}[1]{{\bf [ FIXME: #1 ]}} -\newcommand{\todo}[1]{\marginpar{\footnotesize #1}} - -\newcommand{\wunits}[2]{\mbox{#1\,#2}} -\newcommand{\um}{\mbox{$\mu$m}} -\newcommand{\xum}[1]{\wunits{#1}{\um}} -\newcommand{\by}[2]{\mbox{#1$\times$#2}} -\newcommand{\byby}[3]{\mbox{#1$\times$#2$\times$#3}} - -\newlength\savedwidth -\newcommand\whline[1]{% - \noalign{% - \global\savedwidth\arrayrulewidth\global\arrayrulewidth 1.5pt% - }% - \cline{#1}% - \noalign{\vskip\arrayrulewidth}% - \noalign{\global\arrayrulewidth\savedwidth}% -} - -% Custom list environments - -\newlist{tightlist}{itemize}{1} -\setlist[tightlist]{label=\textbullet,nosep} - -\newenvironment{titledtightlist}[1] -{\noindent - ~~\textbf{#1} - \begin{tightlist}} -{\end{tightlist}} - -\newenvironment{commentary} -{ \vspace{-1.5mm} - \list{}{ - \topsep 0mm - \partopsep 0mm - \listparindent 1.5em - \itemindent \listparindent - \rightmargin \leftmargin - \parsep 0mm - } - \item - \small\em - \noindent\nopagebreak\rule{\linewidth}{1pt}\par - \noindent\ignorespaces -} -{\endlist} - -%\newenvironment{discussion} -%{ \vspace{-1.5mm} -% \list{}{ -% \topsep 0mm -% \partopsep 0mm -% \listparindent 1.5em -% \itemindent \listparindent -% \rightmargin \leftmargin -% \parsep 0mm -% } -% \item -% \small\em -% \noindent\nopagebreak\rule{\linewidth}{1pt}\par -% \noindent\textbf{Discussion:} -%} -%{\endlist} - -% Other commands and parameters - -\pagestyle{myheadings} -\setlength{\parindent}{0in} -\setlength{\parskip}{10pt} -\sloppy -\raggedbottom -\clubpenalty=10000 -\widowpenalty=10000 - -% Commands for register format figures. - -% New column types to use in tabular environment for instruction formats. -% Allocate 0.18in per bit. -\newcolumntype{I}{>{\centering\arraybackslash}p{0.18in}} -% Two-bit centered column. -\newcolumntype{W}{>{\centering\arraybackslash}p{0.36in}} -% Three-bit centered column. -\newcolumntype{F}{>{\centering\arraybackslash}p{0.54in}} -% Four-bit centered column. -\newcolumntype{Y}{>{\centering\arraybackslash}p{0.72in}} -% Five-bit centered column. -\newcolumntype{R}{>{\centering\arraybackslash}p{0.9in}} -% Six-bit centered column. -\newcolumntype{S}{>{\centering\arraybackslash}p{1.08in}} -% Seven-bit centered column. -\newcolumntype{O}{>{\centering\arraybackslash}p{1.26in}} -% Eight-bit centered column. -\newcolumntype{E}{>{\centering\arraybackslash}p{1.44in}} -% Ten-bit centered column. -\newcolumntype{T}{>{\centering\arraybackslash}p{1.8in}} -% Twelve-bit centered column. -\newcolumntype{M}{>{\centering\arraybackslash}p{2.2in}} -% Sixteen-bit centered column. -\newcolumntype{K}{>{\centering\arraybackslash}p{2.88in}} -% Twenty-bit centered column. -\newcolumntype{U}{>{\centering\arraybackslash}p{3.6in}} -% Twenty-bit centered column. -\newcolumntype{L}{>{\centering\arraybackslash}p{3.6in}} -% Twenty-five-bit centered column. -\newcolumntype{J}{>{\centering\arraybackslash}p{4.5in}} - -\newcommand{\instbit}[1]{\mbox{\scriptsize #1}} -\newcommand{\instbitrange}[2]{~\instbit{#1} \hfill \instbit{#2}~} -\newcommand{\reglabel}[1]{\hfill {\tt #1}\hfill\ } - -\newcommand{\wiri}{\textbf{WIRI}} -\newcommand{\wpri}{\textbf{WPRI}} -\newcommand{\wlrl}{\textbf{WLRL}} -\newcommand{\warl}{\textbf{WARL}} - -\newcommand{\unspecified}{\textsc{unspecified}} diff --git a/libresoc-isa-manual/powerpc-add/src/preface.tex b/libresoc-isa-manual/powerpc-add/src/preface.tex deleted file mode 100644 index baa330d..0000000 --- a/libresoc-isa-manual/powerpc-add/src/preface.tex +++ /dev/null @@ -1,5 +0,0 @@ -\chapter{Preface} - -This document describes the Libre-SOC ISAMUX additions to the PowerPC architecture. - -\cite{foo-bar} diff --git a/powerpc-add/.gitignore b/powerpc-add/.gitignore index ea1472e..4f058f9 100644 --- a/powerpc-add/.gitignore +++ b/powerpc-add/.gitignore @@ -1 +1,2 @@ output/ +NOTES diff --git a/powerpc-add/src/atomics.tex b/powerpc-add/src/atomics.tex new file mode 100644 index 0000000..b1301af --- /dev/null +++ b/powerpc-add/src/atomics.tex @@ -0,0 +1,2 @@ +% C++ Atomics +% https://bugs.libre-soc.org/show_bug.cgi?id=236 diff --git a/powerpc-add/src/fp16.tex b/powerpc-add/src/fp16.tex new file mode 100644 index 0000000..9788ee4 --- /dev/null +++ b/powerpc-add/src/fp16.tex @@ -0,0 +1,2 @@ +% Write-up of the augmentation of POWER ISA to switch on IEEE754 FP16 +% https://bugs.libre-soc.org/show_bug.cgi?id=239 diff --git a/powerpc-add/src/glossary.tex b/powerpc-add/src/glossary.tex index 5aed0b3..941adf2 100644 --- a/powerpc-add/src/glossary.tex +++ b/powerpc-add/src/glossary.tex @@ -125,6 +125,15 @@ } } +\newglossaryentry{ICubeCorpIC3128} +{ + name=ICubeCorp IC3128, + description={ + A \gls{SoC} from ICube that has both \gls{CPU} and \gls{GPU} on a single chip. + See: \href{https://www.cnx-software.com/2014/10/15/icube-mvp-socs-combine-cpu-and-gpu-into-a-single-unified-processing-unit-upu/}{CNX Software} + } +} + \newglossaryentry{IEEE754} { name=IEEE754, @@ -136,6 +145,17 @@ } } +\newglossaryentry{IOMMU} +{ + name=IOMMU, + description={ + Input Output Memory Management Unit. + Mediates between Input/Output devices and main memory mapping virtual + addresses to physical ones and, maybe, enforcing protection restrictions. + See: \href{https://en.wikipedia.org/wiki/Input%E2%80%93output_memory_management_unit}{Wikipedia} + } +} + \newglossaryentry{ISA} { name=ISA, @@ -148,6 +168,28 @@ } } +\newglossaryentry{ISAMUX} +{ + name=ISAMUX, + description={ + \gls{ISA} \gls{MUX} -- having the same bits in the ISA mean different things. + } +} + +\newglossaryentry{H.265} +{ + name=H.265, + description={ + High Efficiency Video Coding, also known as HEVC \& MPEG-H Part 2. + Released in 2013. + Its data compression is better, for the same video quality, than previous standards: + AVC, H.264, or MPEG-4 Part 10. + Patent license may be required for H.265 use. + See: \gls{VP9} + \href{https://en.wikipedia.org/wiki/High_Efficiency_Video_Coding}{Wikipedia} + } +} + \newglossaryentry{JIT} { name=JIT, @@ -183,6 +225,29 @@ } } +\newglossaryentry{MISA} +{ + name=MISA, + description={ + Multiple Instruction Sets Architecture. + The ability to run more than one \gls{ISA} on the same hardware. + A setting in a \gls{CSR} controls which instructions will be + recognised at any time. + See: \href{}{} + } +} +% https://ieeexplore.ieee.org/document/6136696 - paywalled +% https://www.researchgate.net/figure/Overview-of-the-MISA-instructional-system-design-method_fig2_245165034 +% https://people.eecs.berkeley.edu/~krste/papers/riscv-privileged-v1.9.pdf page 15 + +\newglossaryentry{MUX} +{ + name=MUX, + description={ + Multiplex, a way of compressing several things into the same data. +% See: \href{}{} + } +} \newglossaryentry{PowerPC} { @@ -245,12 +310,33 @@ } } +\newglossaryentry{VideoCoreIV} +{ + name=VideoCore IV, + description={ + Low power \gls{SoC} from Broadcom. ARM CPU that is used in the Raspberry Pi. + See: \href{https://en.wikipedia.org/wiki/VideoCore}{Wikipedia} + } +} + +\newglossaryentry{VP9} +{ + name=VP9, + description={ + Video encoding format released by Google in 2013. + Released open \& royalty free although Sisvel has made some claims. + See: \href{https://en.wikipedia.org/wiki/VP9}{Wikipedia} + } +} + +% https://libre-soc.org/vpu/ \newglossaryentry{VPU} { name=VPU, description={ - Video Processing Unit and Visual Processing Unit and Vector Processing Unit - Contrast with \gls{CPU} and \gls{GPU}. + Video Processing Unit. + Similar to a \gls{CPU} but has extra hardware instructions to speed up things + like the decoding and encoding of \gls{H.265}, or \gls{VP9}. % See: \href{}{} } } @@ -270,8 +356,23 @@ % namespace % MSB % PCR +% SIMD +% ALU +% RA +% RB +% microwatt https://github.com/antonblanchard/microwatt/blob/master/decode1.vhdl +% 6600 https://libre-soc.org/3d_gpu/architecture/6600scoreboard/ +% DAG Directed Acyclic Graph +% SR latch +% FU Functional Unit +% FPU float point unit +% WAR https://libre-soc.org/3d_gpu/architecture/6600scoreboard/ #10 +% ALU +% FU-FU function to function https://libre-soc.org/3d_gpu/architecture/6600scoreboard/ #14 +% GORD GOWR GO read/write % ISANS +% Unified Processing Unit (UPU) +% MVP (Multi-thread Virtual Pipeline % SIE -% MISA % WARL % WLRL diff --git a/powerpc-add/src/intro.tex b/powerpc-add/src/intro.tex index d1710a6..98032de 100644 --- a/powerpc-add/src/intro.tex +++ b/powerpc-add/src/intro.tex @@ -143,7 +143,7 @@ There is no separate VPU, because the CPU is the GPU. There is not even a separate pipeline: the CPU pipelines are the GPU and VPU pipelines. Closest equivalents include the ARC core (which has VPU extensions and 3D -extensions in the form of Broadcom's VideoCore IV) and the ICubeCorp IC3128. +extensions in the form of Broadcom's \gls{VideoCoreIV}) and the \gls{ICubeCorpIC3128}. Both are considered \textbf{hybrid} CPU-GPU-VPU processors. \textbf{Normal} Commercial GPUs are entirely separate processors. The development cost diff --git a/powerpc-add/src/isa_op_protocol.tex b/powerpc-add/src/isa_op_protocol.tex new file mode 100644 index 0000000..a49a4d5 --- /dev/null +++ b/powerpc-add/src/isa_op_protocol.tex @@ -0,0 +1,2 @@ +% Write-up of a suitable compressed ISA Opcode protocol +% https://bugs.libre-soc.org/show_bug.cgi?id=238 diff --git a/powerpc-add/src/isamux.tex b/powerpc-add/src/isamux.tex index 79da4ea..8d7a485 100644 --- a/powerpc-add/src/isamux.tex +++ b/powerpc-add/src/isamux.tex @@ -1,4 +1,5 @@ % ISAMUX +% https://bugs.libre-soc.org/show_bug.cgi?id=214 \chapter{Introduction} @@ -382,7 +383,7 @@ trap_exit(x_cause): } \end{verbatim} -\subsection{Is this like MISA?} \label{misa} +\subsection{Is this like \gls{MISA} ?} \label{misa} \paragraph{} @@ -402,7 +403,7 @@ There is no allocation (provision) for custom extensions. \item -MISA switches on and off entire extensions: ISAMUX/NS may be used to switch +MISA switches on and off entire extensions: \gls{ISAMUX}/NS may be used to switch multiple opcodes (present and future), to alternate meanings. \item diff --git a/powerpc-add/src/power-spec.tex b/powerpc-add/src/power-spec.tex index 9476f36..86514f4 100644 --- a/powerpc-add/src/power-spec.tex +++ b/powerpc-add/src/power-spec.tex @@ -54,6 +54,11 @@ Alain Williams, Libre-SOC, \specmonthyear. \input{intro} \input{isamux} +\input{atomics} +\input{varenc} +\input{isa_op_protocol} +% https://bugs.libre-soc.org/show_bug.cgi?id=238 +\input{fp16} % \input{rv32} % \input{zifencei} diff --git a/powerpc-add/src/varenc.tex b/powerpc-add/src/varenc.tex new file mode 100644 index 0000000..99fbbae --- /dev/null +++ b/powerpc-add/src/varenc.tex @@ -0,0 +1,2 @@ +% Write-up of the Variable-sized Opcode protocol +% https://bugs.libre-soc.org/show_bug.cgi?id=174 -- 2.30.2