From d6da4c257be2eafcbebc3f956ca09c0aabf092bd Mon Sep 17 00:00:00 2001 From: whitequark Date: Tue, 10 Nov 2020 05:30:21 +0000 Subject: [PATCH] =?utf8?q?build.plat:=20TemplatedPlatform.iter=5Fextra=5Ff?= =?utf8?q?iles=E2=86=92Platform.iter=5Ffiles.?= MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit This function was added in commit 20553b14 in the wrong place, with the wrong name, and without tests. Fix all that. --- nmigen/build/plat.py | 8 +++++--- nmigen/vendor/intel.py | 6 +++--- nmigen/vendor/lattice_ecp5.py | 8 ++++---- nmigen/vendor/lattice_ice40.py | 10 +++++----- nmigen/vendor/lattice_machxo_2_3l.py | 2 +- nmigen/vendor/quicklogic.py | 2 +- nmigen/vendor/xilinx_7series.py | 6 +++--- nmigen/vendor/xilinx_spartan_3_6.py | 4 ++-- nmigen/vendor/xilinx_ultrascale.py | 4 ++-- tests/test_build_plat.py | 11 +++++++++++ 10 files changed, 37 insertions(+), 24 deletions(-) diff --git a/nmigen/build/plat.py b/nmigen/build/plat.py index 31c9704..750a477 100644 --- a/nmigen/build/plat.py +++ b/nmigen/build/plat.py @@ -63,6 +63,11 @@ class Platform(ResourceManager, metaclass=ABCMeta): else: self.extra_files[filename] = content + def iter_files(self, *suffixes): + for filename in self.extra_files: + if filename.endswith(suffixes): + yield filename + @property def _toolchain_env_var(self): return f"NMIGEN_ENV_{self.toolchain}" @@ -437,6 +442,3 @@ class TemplatedPlatform(Platform): for filename, content in self.extra_files.items(): plan.add_file(filename, content) return plan - - def iter_extra_files(self, *endswith): - return (f for f in self.extra_files if f.endswith(endswith)) diff --git a/nmigen/vendor/intel.py b/nmigen/vendor/intel.py index 8393dea..dc1f1bc 100644 --- a/nmigen/vendor/intel.py +++ b/nmigen/vendor/intel.py @@ -82,13 +82,13 @@ class IntelPlatform(TemplatedPlatform): set_global_assignment -name NUM_PARALLEL_PROCESSORS {{get_override("nproc")}} {% endif %} - {% for file in platform.iter_extra_files(".v") -%} + {% for file in platform.iter_files(".v") -%} set_global_assignment -name VERILOG_FILE {{file|tcl_quote}} {% endfor %} - {% for file in platform.iter_extra_files(".sv") -%} + {% for file in platform.iter_files(".sv") -%} set_global_assignment -name SYSTEMVERILOG_FILE {{file|tcl_quote}} {% endfor %} - {% for file in platform.iter_extra_files(".vhd", ".vhdl") -%} + {% for file in platform.iter_files(".vhd", ".vhdl") -%} set_global_assignment -name VHDL_FILE {{file|tcl_quote}} {% endfor %} set_global_assignment -name VERILOG_FILE {{name}}.v diff --git a/nmigen/vendor/lattice_ecp5.py b/nmigen/vendor/lattice_ecp5.py index 2a68dad..2775c91 100644 --- a/nmigen/vendor/lattice_ecp5.py +++ b/nmigen/vendor/lattice_ecp5.py @@ -112,13 +112,13 @@ class LatticeECP5Platform(TemplatedPlatform): """, "{{name}}.ys": r""" # {{autogenerated}} - {% for file in platform.iter_extra_files(".v") -%} + {% for file in platform.iter_files(".v") -%} read_verilog {{get_override("read_verilog_opts")|options}} {{file}} {% endfor %} - {% for file in platform.iter_extra_files(".sv") -%} + {% for file in platform.iter_files(".sv") -%} read_verilog -sv {{get_override("read_verilog_opts")|options}} {{file}} {% endfor %} - {% for file in platform.iter_extra_files(".il") -%} + {% for file in platform.iter_files(".il") -%} read_ilang {{file}} {% endfor %} read_ilang {{name}}.il @@ -210,7 +210,7 @@ class LatticeECP5Platform(TemplatedPlatform): -dev {{platform.device}}-{{platform.speed}}{{platform.package}}{{platform.grade}} \ -lpf {{name}}.lpf \ -synthesis synplify - {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%} + {% for file in platform.iter_files(".v", ".sv", ".vhd", ".vhdl") -%} prj_src add {{file|tcl_escape}} {% endfor %} prj_src add {{name}}.v diff --git a/nmigen/vendor/lattice_ice40.py b/nmigen/vendor/lattice_ice40.py index 4e6b282..c9c35b3 100644 --- a/nmigen/vendor/lattice_ice40.py +++ b/nmigen/vendor/lattice_ice40.py @@ -114,13 +114,13 @@ class LatticeICE40Platform(TemplatedPlatform): """, "{{name}}.ys": r""" # {{autogenerated}} - {% for file in platform.iter_extra_files(".v") -%} + {% for file in platform.iter_files(".v") -%} read_verilog {{get_override("read_verilog_opts")|options}} {{file}} {% endfor %} - {% for file in platform.iter_extra_files(".sv") -%} + {% for file in platform.iter_files(".sv") -%} read_verilog -sv {{get_override("read_verilog_opts")|options}} {{file}} {% endfor %} - {% for file in platform.iter_extra_files(".il") -%} + {% for file in platform.iter_files(".il") -%} read_ilang {{file}} {% endfor %} read_ilang {{name}}.il @@ -212,7 +212,7 @@ class LatticeICE40Platform(TemplatedPlatform): -d {{platform.device}} -t {{platform.package}} {{get_override("lse_opts")|options|default("# (lse_opts placeholder)")}} - {% for file in platform.iter_extra_files(".v") -%} + {% for file in platform.iter_files(".v") -%} -ver {{file}} {% endfor %} -ver {{name}}.v @@ -223,7 +223,7 @@ class LatticeICE40Platform(TemplatedPlatform): """, "{{name}}_syn.prj": r""" # {{autogenerated}} - {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%} + {% for file in platform.iter_files(".v", ".sv", ".vhd", ".vhdl") -%} add_file -verilog {{file|tcl_escape}} {% endfor %} add_file -verilog {{name}}.v diff --git a/nmigen/vendor/lattice_machxo_2_3l.py b/nmigen/vendor/lattice_machxo_2_3l.py index 08c6008..64aa193 100644 --- a/nmigen/vendor/lattice_machxo_2_3l.py +++ b/nmigen/vendor/lattice_machxo_2_3l.py @@ -74,7 +74,7 @@ class LatticeMachXO2Or3LPlatform(TemplatedPlatform): -dev {{platform.device}}-{{platform.speed}}{{platform.package}}{{platform.grade}} \ -lpf {{name}}.lpf \ -synthesis synplify - {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%} + {% for file in platform.iter_files(".v", ".sv", ".vhd", ".vhdl") -%} prj_src add {{file|tcl_escape}} {% endfor %} prj_src add {{name}}.v diff --git a/nmigen/vendor/quicklogic.py b/nmigen/vendor/quicklogic.py index c8bd5cb..6e9c63c 100644 --- a/nmigen/vendor/quicklogic.py +++ b/nmigen/vendor/quicklogic.py @@ -82,7 +82,7 @@ class QuicklogicPlatform(TemplatedPlatform): r""" {{invoke_tool("symbiflow_synth")}} -t {{name}} - -v {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%} {{file}} {% endfor %} {{name}}.v + -v {% for file in platform.iter_files(".v", ".sv", ".vhd", ".vhdl") -%} {{file}} {% endfor %} {{name}}.v -d {{platform.device}} -p {{name}}.pcf -P {{platform.package}} diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py index 9dd738c..084d2ba 100644 --- a/nmigen/vendor/xilinx_7series.py +++ b/nmigen/vendor/xilinx_7series.py @@ -99,12 +99,12 @@ class Xilinx7SeriesPlatform(TemplatedPlatform): "{{name}}.tcl": r""" # {{autogenerated}} create_project -force -name {{name}} -part {{platform._part}} - {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%} + {% for file in platform.iter_files(".v", ".sv", ".vhd", ".vhdl") -%} add_files {{file|tcl_escape}} {% endfor %} add_files {{name}}.v read_xdc {{name}}.xdc - {% for file in platform.iter_extra_files(".xdc") -%} + {% for file in platform.iter_files(".xdc") -%} read_xdc {{file|tcl_escape}} {% endfor %} {{get_override("script_after_read")|default("# (script_after_read placeholder)")}} @@ -229,7 +229,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform): r""" {{invoke_tool("synth")}} -t {{name}} - -v {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%} {{file}} {% endfor %} {{name}}.v + -v {% for file in platform.iter_files(".v", ".sv", ".vhd", ".vhdl") -%} {{file}} {% endfor %} {{name}}.v -p {{platform._symbiflow_part_map.get(platform._part, platform._part)}} -x {{name}}.xdc """, diff --git a/nmigen/vendor/xilinx_spartan_3_6.py b/nmigen/vendor/xilinx_spartan_3_6.py index 9b10733..527d089 100644 --- a/nmigen/vendor/xilinx_spartan_3_6.py +++ b/nmigen/vendor/xilinx_spartan_3_6.py @@ -102,10 +102,10 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform): """, "{{name}}.prj": r""" # {{autogenerated}} - {% for file in platform.iter_extra_files(".vhd", ".vhdl") -%} + {% for file in platform.iter_files(".vhd", ".vhdl") -%} vhdl work {{file}} {% endfor %} - {% for file in platform.iter_extra_files(".v") -%} + {% for file in platform.iter_files(".v") -%} verilog work {{file}} {% endfor %} verilog work {{name}}.v diff --git a/nmigen/vendor/xilinx_ultrascale.py b/nmigen/vendor/xilinx_ultrascale.py index 0969ccb..bc28ac2 100644 --- a/nmigen/vendor/xilinx_ultrascale.py +++ b/nmigen/vendor/xilinx_ultrascale.py @@ -73,12 +73,12 @@ class XilinxUltraScalePlatform(TemplatedPlatform): "{{name}}.tcl": r""" # {{autogenerated}} create_project -force -name {{name}} -part {{platform.device}}-{{platform.package}}-{{platform.speed}} - {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%} + {% for file in platform.iter_files(".v", ".sv", ".vhd", ".vhdl") -%} add_files {{file|tcl_escape}} {% endfor %} add_files {{name}}.v read_xdc {{name}}.xdc - {% for file in platform.iter_extra_files(".xdc") -%} + {% for file in platform.iter_files(".xdc") -%} read_xdc {{file|tcl_escape}} {% endfor %} {{get_override("script_after_read")|default("# (script_after_read placeholder)")}} diff --git a/tests/test_build_plat.py b/tests/test_build_plat.py index 31dc5c9..76a5331 100644 --- a/tests/test_build_plat.py +++ b/tests/test_build_plat.py @@ -51,3 +51,14 @@ class PlatformTestCase(FHDLTestCase): with self.assertRaisesRegex(ValueError, r"^File 'foo' already exists$"): self.platform.add_file("foo", "bar") + + def test_iter_files(self): + self.platform.add_file("foo.v", "") + self.platform.add_file("bar.v", "") + self.platform.add_file("baz.vhd", "") + self.assertEqual(list(self.platform.iter_files(".v")), + ["foo.v", "bar.v"]) + self.assertEqual(list(self.platform.iter_files(".vhd")), + ["baz.vhd"]) + self.assertEqual(list(self.platform.iter_files(".v", ".vhd")), + ["foo.v", "bar.v", "baz.vhd"]) -- 2.30.2