From d6e7180f0ec5a148db4b171203f596b62f9c5e05 Mon Sep 17 00:00:00 2001 From: Shriya Sharma Date: Thu, 19 Oct 2023 11:16:53 +0100 Subject: [PATCH] added lbzsux instruction refer to https://bugs.libre-soc.org/show_bug.cgi?id=1055 --- openpower/isa/fixedloadshift.mdwn | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/openpower/isa/fixedloadshift.mdwn b/openpower/isa/fixedloadshift.mdwn index bc488ad0..45827e77 100644 --- a/openpower/isa/fixedloadshift.mdwn +++ b/openpower/isa/fixedloadshift.mdwn @@ -30,12 +30,12 @@ X-Form -* lbzsx RT,RA,RB,sh +* lbzsx RT,RA,RB,sm Pseudo-code: b <- (RA|0) - EA <- b + (RB) << (sh+1) + EA <- b + (RB) << (sm+1) RT <- ([0] * (XLEN-8)) || MEM(EA, 1) Special Registers Altered: @@ -46,11 +46,11 @@ Special Registers Altered: X-Form -* lbzsux RT,RA,RB,sh +* lbzsux RT,RA,RB,sm Pseudo-code: - EA <- (RA) + (RB) << (sh+1) + EA <- (RA) + (RB) << (sm+1) RT <- ([0] * (XLEN-8)) || MEM(EA, 1) RA <- EA @@ -58,16 +58,16 @@ Special Registers Altered: None -# Load Halfword and Zero Indexed +# Load Halfword and Zero Shifted Indexed X-Form -* lhzx RT,RA,RB +* lhzsx RT,RA,RB,sm Pseudo-code: b <- (RA|0) - EA <- b + (RB) + EA <- b + (RB) (sm+1) RT <- ([0] * (XLEN-16)) || MEM(EA, 2) Special Registers Altered: -- 2.30.2