From d6f10932ff7604a147ab6c02ee19813393caddd2 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 21 Feb 2020 13:00:38 +0000
Subject: [PATCH] deal with zero-width ShiftMask

---
 src/ieee754/part_mul_add/adder.py            | 2 +-
 src/ieee754/part_shift/part_shift_dynamic.py | 5 +++++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/ieee754/part_mul_add/adder.py b/src/ieee754/part_mul_add/adder.py
index c02883c9..e1849b4d 100644
--- a/src/ieee754/part_mul_add/adder.py
+++ b/src/ieee754/part_mul_add/adder.py
@@ -268,6 +268,6 @@ class PartitionedAdder(Elaboratable):
         # in [the LSB of each partition].
         comb += ripple.results_in.eq(carry_tmp)
         comb += ripple.gates.eq(self.part_pts.as_sig())
-        comb += self.carry_out.eq(ripple.output)
+        m.d.sync += self.carry_out.eq(ripple.output)
 
         return m
diff --git a/src/ieee754/part_shift/part_shift_dynamic.py b/src/ieee754/part_shift/part_shift_dynamic.py
index 45ba08ca..c051397b 100644
--- a/src/ieee754/part_shift/part_shift_dynamic.py
+++ b/src/ieee754/part_shift/part_shift_dynamic.py
@@ -29,6 +29,11 @@ class ShifterMask(Elaboratable):
         m = Module()
         comb = m.d.comb
 
+        # zero-width mustn't try to do anything
+        if self.pwid == 0:
+            self.mask.eq((1<<min_bits)-1)
+            return m
+
         bits = Signal(self.pwid, reset_less=True)
         bl = []
         for j in range(self.pwid):
-- 
2.30.2