From d71076d41ceacdc349874cc3a12573d3a66830bd Mon Sep 17 00:00:00 2001 From: Hsuan Hsu Date: Fri, 14 Feb 2020 18:32:46 +0800 Subject: [PATCH] cpu-o3: Fix corrupted rename map in vector mode switching This patch fixes the AArch32-AArch64 interprocessing issue introduced in 3d15150d cpu, arch, arch-arm: Wire unused VecElem code in the O3 model. When O3CPU switches vector renaming mode, architectural-physical mapping and physical free list are switched in the following way so that content of vectors has no change from software view: Case 1. Full mode -> Elem mode (AArch64 -> AArch32): 1.1. Split vector-vector mapping into element-element mapping. 1.2. Split vectors in free list into elements. Case 2. Elem mode -> Full mode (AArch32 -> AArch64): 2.1. Move content of all N*M mapped physical elements to first N*M physical elements in architectural order (N = number of architectural vectors, M = number of elements per vector). 2.2. Map N architectural vectors to first N physical vectors (i.e. initial mapping in full mode). 2.3. Place remaining physical vectors in free list (i.e. initial free list in full mode). Previous gem5 revision misses step 2.2 when AArch32->AArch64 switch. The wrong mapping will lead to the situation in which a physical vector is assigned twice to a same architectural vector without being freed. Once this occurs, the physical vector will not be freed anymore, since it is treated as a special register (e.g. zero or misc) by O3CPU's renaming logic. Eventually O3CPU will either stall forever when all physical vectors get stuck, or trigger the panic condition "The free list has lost vector registers" when AArch64->AArch32 switch. This patch adds the missing step and fixes the issue. Change-Id: I32233635c28763260bcbb776b52ed198a9abace9 Signed-off-by: Hsuan Hsu Signed-off-by: Howard Wang Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25743 Reviewed-by: Jason Lowe-Power Reviewed-by: Giacomo Travaglini Maintainer: Jason Lowe-Power Maintainer: Giacomo Travaglini Tested-by: kokoro --- src/cpu/o3/rename_map.cc | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/cpu/o3/rename_map.cc b/src/cpu/o3/rename_map.cc index fdb98940f..dbea832ef 100644 --- a/src/cpu/o3/rename_map.cc +++ b/src/cpu/o3/rename_map.cc @@ -215,5 +215,10 @@ UnifiedRenameMap::switchMode(VecMode newVecMode) regFile->setVecReg(regFile->getTrueId(&pregId), new_RF[i]); } + auto range = regFile->getRegIds(VecRegClass); + for (uint32_t i = 0; i < TheISA::NumVecRegs; i++) { + setEntry(RegId(VecRegClass, i), &(*(range.first + i))); + } + } } -- 2.30.2