From d7141d8bc0d534a1a79a2285ac6cda3838ca872e Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Tue, 6 Jun 2017 12:13:40 +0200 Subject: [PATCH] radeonsi/gfx9: indirect buffers and all CP packets use TC L2 MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_compute.c | 5 +++-- src/gallium/drivers/radeonsi/si_pipe.c | 6 ++++-- src/gallium/drivers/radeonsi/si_state.c | 4 +++- src/gallium/drivers/radeonsi/si_state_draw.c | 19 +++++++++++-------- 4 files changed, 21 insertions(+), 13 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c index 79b107e96fc..65f3261e0a1 100644 --- a/src/gallium/drivers/radeonsi/si_compute.c +++ b/src/gallium/drivers/radeonsi/si_compute.c @@ -788,8 +788,9 @@ static void si_launch_grid( if (info->indirect) { r600_context_add_resource_size(ctx, info->indirect); - /* The hw doesn't read the indirect buffer via TC L2. */ - if (r600_resource(info->indirect)->TC_L2_dirty) { + /* Indirect buffers use TC L2 on GFX9, but not older hw. */ + if (sctx->b.chip_class <= VI && + r600_resource(info->indirect)->TC_L2_dirty) { sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; r600_resource(info->indirect)->TC_L2_dirty = false; } diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index fda615e30c4..d2ba8df00db 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -1010,8 +1010,10 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws) (sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0; sscreen->b.barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 | - SI_CONTEXT_INV_VMEM_L1 | - SI_CONTEXT_INV_GLOBAL_L2; + SI_CONTEXT_INV_VMEM_L1; + if (sscreen->b.chip_class <= VI) + sscreen->b.barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_GLOBAL_L2; + sscreen->b.barrier_flags.compute_to_L2 = SI_CONTEXT_CS_PARTIAL_FLUSH; if (debug_get_bool_option("RADEON_DUMP_SHADERS", false)) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index a0d790ac2a9..0f39ede0c7e 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -4023,7 +4023,9 @@ static void si_memory_barrier(struct pipe_context *ctx, unsigned flags) SI_CONTEXT_WRITEBACK_GLOBAL_L2; } - if (flags & PIPE_BARRIER_INDIRECT_BUFFER) + /* Indirect buffers use TC L2 on GFX9, but not older hw. */ + if (sctx->screen->b.chip_class <= VI && + flags & PIPE_BARRIER_INDIRECT_BUFFER) sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; } diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index d13c8b7086f..2b000e74696 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -1320,15 +1320,18 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) /* Add the buffer size for memory checking in need_cs_space. */ r600_context_add_resource_size(ctx, indirect->buffer); - if (r600_resource(indirect->buffer)->TC_L2_dirty) { - sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; - r600_resource(indirect->buffer)->TC_L2_dirty = false; - } + /* Indirect buffers use TC L2 on GFX9, but not older hw. */ + if (sctx->b.chip_class <= VI) { + if (r600_resource(indirect->buffer)->TC_L2_dirty) { + sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; + r600_resource(indirect->buffer)->TC_L2_dirty = false; + } - if (indirect->indirect_draw_count && - r600_resource(indirect->indirect_draw_count)->TC_L2_dirty) { - sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; - r600_resource(indirect->indirect_draw_count)->TC_L2_dirty = false; + if (indirect->indirect_draw_count && + r600_resource(indirect->indirect_draw_count)->TC_L2_dirty) { + sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; + r600_resource(indirect->indirect_draw_count)->TC_L2_dirty = false; + } } } -- 2.30.2