From d72ff03e699e78381049e29d89163519e6730dd4 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 12 Jul 2012 12:48:58 -0700 Subject: [PATCH] i965: Add INTEL_DEBUG=perf for failure to compile 16-wide shaders. Reviewed-by: Jordan Justen Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_fs.cpp | 5 ++++- src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 3 ++- src/mesa/drivers/dri/intel/intel_context.h | 5 +++++ 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index e8ee0cb8f7e..334a14c25d5 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -2096,7 +2096,10 @@ brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c, c->dispatch_width = 16; fs_visitor v2(c, prog, shader); v2.import_uniforms(&v); - v2.run(); + if (!v2.run()) { + perf_debug("16-wide shader failed to compile, falling back to " + "8-wide at a 10-20%% performance cost: %s", v2.fail_msg); + } } c->prog_data.dispatch_width = 8; diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp index 7618047df58..e7f11aee0df 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp @@ -238,7 +238,8 @@ fs_visitor::assign_regs() if (reg == -1) { fail("no register to spill\n"); } else if (c->dispatch_width == 16) { - fail("no spilling support on 16-wide yet\n"); + fail("Failure to register allocate. Reduce number of live scalar " + "values to avoid this."); } else { spill_reg(reg); } diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h index 49db119b6e9..063cc34acee 100644 --- a/src/mesa/drivers/dri/intel/intel_context.h +++ b/src/mesa/drivers/dri/intel/intel_context.h @@ -464,6 +464,11 @@ extern int INTEL_DEBUG; printf(__VA_ARGS__); \ } while(0) +#define perf_debug(...) do { \ + if (unlikely(INTEL_DEBUG & DEBUG_PERF)) \ + printf(__VA_ARGS__); \ +} while(0) + #define PCI_CHIP_845_G 0x2562 #define PCI_CHIP_I830_M 0x3577 #define PCI_CHIP_I855_GM 0x3582 -- 2.30.2